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AD7607BSTZ

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Analog Devices ADCs/DACs - Special Purpose, LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AD7607BSTZ

Analog Devices · ADCs/DACs - Special Purpose · LQFP-64(10x10)

AD7607BSTZ from Analog Devices, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AVCC power_in Analog supply of 4.75 V to 5.25 V that powers the internal front-end amplifiers and ADC core and must be decoupled to AGND.
2 AGND power_in Analog ground reference for all analog circuitry and analog input and external reference signals; all six AGND pins must connect to the system AGND plane.
3 OS0 input Oversampling mode select LSB, latched on the BUSY falling edge to set the oversampling ratio for the next conversion per Table 9.
4 OS1 input Oversampling mode select bit 1, latched on the BUSY falling edge to set the oversampling ratio for the next conversion per Table 9.
5 OS2 input Oversampling mode select MSB, latched on the BUSY falling edge together with OS1 and OS0 to set the oversampling ratio per Table 9.
6 PAR/SER/BYTE SEL input Interface select: logic low selects the parallel interface, logic high selects the serial interface (DB15/BYTE SEL low) or the parallel byte interface (DB15/BYTE SEL high).
7 STBY input Standby input that, when low, selects standby (RANGE high) or shutdown (RANGE low) power-saving mode per Table 7.
8 RANGE input Analog input range select for all channels: logic high selects ±10 V and logic low selects ±5 V, and the pin should not be changed during conversion.
9 CONVST A input Conversion start input A; its rising edge holds the V1-V4 track-and-hold, and with CONVST B tied together it starts simultaneous sampling of all eight channels.
10 CONVST B input Conversion start input B; its rising edge holds the V5-V8 track-and-hold, and the maximum allowed delay between the CONVST A and CONVST B rising edges is 0.5 ms (t5).
11 RESET input Active-high reset that must be pulsed after power-up with a minimum high pulse of 50 ns (tRESET); applying it during a conversion aborts the conversion.
12 RD/SCLK input Parallel read control input RD when the parallel interface is selected, or serial clock input SCLK when the serial interface is selected.
13 CS input Active-low chip select that enables the data frame; in parallel mode CS and RD low enable DB[15:0], and in serial mode CS frames the transfer.
14 BUSY output Goes high on the CONVST rising edge and returns low when all channels finish converting, and its falling edge indicates results can be read after t4.
15 FRSTDATA output Indicates when channel V1 is being read on the parallel, byte or serial interface and is tri-stated while CS is high.
16 DB0 tri_state Parallel data output bit 0 (LSB), tri-stated unless CS and RD are low, and tied to digital ground when PAR/SER/BYTE SEL is high.
17 DB1 tri_state Parallel data output bit 1, tri-stated unless CS and RD are low, and tied to digital ground when PAR/SER/BYTE SEL is high.
18 DB2 tri_state Parallel data output bit 2, tri-stated unless CS and RD are low, and tied to digital ground when PAR/SER/BYTE SEL is high.
19 DB3 tri_state Parallel data output bit 3, tri-stated unless CS and RD are low, and tied to digital ground when PAR/SER/BYTE SEL is high.
20 DB4 tri_state Parallel data output bit 4, tri-stated unless CS and RD are low, and tied to digital ground when PAR/SER/BYTE SEL is high.
21 DB5 tri_state Parallel data output bit 5, tri-stated unless CS and RD are low, and tied to digital ground when PAR/SER/BYTE SEL is high.
22 DB6 tri_state Parallel data output bit 6, tri-stated unless CS and RD are low, and tied to digital ground when PAR/SER/BYTE SEL is high.
23 VDRIVE power_in Logic interface supply of 2.3 V to 5.25 V that sets the digital I/O logic levels and should match the host processor supply.
24 DB7/DOUTA tri_state Parallel data bit 7 (MSB of the byte in byte mode), or serial output DOUTA that carries channels V1-V4 when the serial interface is selected.
25 DB8/DOUTB tri_state Parallel data bit 8, or serial output DOUTB that carries channels V5-V8 when the serial interface is selected.
26 AGND power_in Analog ground pin associated with the analog circuitry; must connect to the system AGND plane.
27 DB9 tri_state Parallel data output bit 9, tri-stated unless CS and RD are low, and tied to digital ground when PAR/SER/BYTE SEL is high.
28 DB10 tri_state Parallel data output bit 10, tri-stated unless CS and RD are low, and tied to digital ground when PAR/SER/BYTE SEL is high.
29 DB11 tri_state Parallel data output bit 11, tri-stated unless CS and RD are low, and tied to digital ground when PAR/SER/BYTE SEL is high.
30 DB12 tri_state Parallel data output bit 12, tri-stated unless CS and RD are low, and tied to digital ground when PAR/SER/BYTE SEL is high.
31 DB13 tri_state Parallel data output bit 13 (MSB of the 14-bit result), tri-stated unless CS and RD are low, and tied to digital ground when PAR/SER/BYTE SEL is high.
32 DB14/HBEN bidirectional Parallel data bit 14 (sign extension of DB13) in parallel mode, or HBEN in byte mode selecting whether the high byte (HBEN high) or low byte (HBEN low) is output first.
33 DB15/BYTE SEL bidirectional Parallel data bit 15 (sign extension) in parallel mode, and with PAR/SER/BYTE SEL high it selects serial (low) or parallel byte (high) interface mode per Table 8.
34 REF SELECT input Reference select: logic high enables the internal 2.5 V reference, while logic low disables it and requires a 2.5 V external reference on REFIN/REFOUT.
35 AGND power_in Analog ground pin for the analog input channels; must connect to the system AGND plane.
36 REGCAP power_out Internal 2.5 V LDO regulator output that must be decoupled to AGND with a 1 µF capacitor and sits at 2.5 V to 2.7 V.
37 AVCC power_in Analog supply of 4.75 V to 5.25 V; may share a decoupling capacitor with pin 38.
38 AVCC power_in Analog supply of 4.75 V to 5.25 V; may share a decoupling capacitor with pin 37.
39 REGCAP power_out Internal 2.5 V LDO regulator output that must be decoupled to AGND with a 1 µF capacitor and sits at 2.5 V to 2.7 V.
40 AGND power_in Analog ground pin for the analog circuitry; must connect to the system AGND plane.
41 AGND power_in Analog ground pin for the analog circuitry; must connect to the system AGND plane.
42 REFIN/REFOUT bidirectional Reference output of 2.5 V when REF SELECT is high or reference input of 2.5 V when REF SELECT is low, and it requires a 10 µF ceramic decoupling capacitor to REFGND.
43 REFGND power_in Reference ground pin that must be connected to AGND.
44 REFCAPA output Reference buffer output force/sense pin that must be shorted to REFCAPB and decoupled to ground with a low-ESR 10 µF ceramic capacitor (buffer amplifies the reference to about 4.5 V).
45 REFCAPB output Reference buffer output force/sense pin that must be shorted to REFCAPA and decoupled to ground with a low-ESR 10 µF ceramic capacitor (buffer amplifies the reference to about 4.5 V).
46 REFGND power_in Reference ground pin that must be connected to AGND.
47 AGND power_in Analog ground pin for the analog circuitry; must connect to the system AGND plane.
48 AVCC power_in Analog supply of 4.75 V to 5.25 V that must be decoupled to AGND.
49 V1 input Single-ended analog input channel 1 with 1 MΩ input impedance, ±10 V or ±5 V range set by RANGE, and clamp protection to ±16.5 V.
50 V1GND power_in Analog input ground for V1; if a series resistor is used on V1, an equal resistor must be placed on V1GND to avoid offset error.
51 V2 input Single-ended analog input channel 2 with 1 MΩ input impedance, ±10 V or ±5 V range set by RANGE, and clamp protection to ±16.5 V.
52 V2GND power_in Analog input ground for V2; if a series resistor is used on V2, an equal resistor must be placed on V2GND to avoid offset error.
53 V3 input Single-ended analog input channel 3 with 1 MΩ input impedance, ±10 V or ±5 V range set by RANGE, and clamp protection to ±16.5 V.
54 V3GND power_in Analog input ground for V3; if a series resistor is used on V3, an equal resistor must be placed on V3GND to avoid offset error.
55 V4 input Single-ended analog input channel 4 with 1 MΩ input impedance, ±10 V or ±5 V range set by RANGE, and clamp protection to ±16.5 V.
56 V4GND power_in Analog input ground for V4; if a series resistor is used on V4, an equal resistor must be placed on V4GND to avoid offset error.
57 V5 input Single-ended analog input channel 5 with 1 MΩ input impedance, ±10 V or ±5 V range set by RANGE, and clamp protection to ±16.5 V.
58 V5GND power_in Analog input ground for V5; if a series resistor is used on V5, an equal resistor must be placed on V5GND to avoid offset error.
59 V6 input Single-ended analog input channel 6 with 1 MΩ input impedance, ±10 V or ±5 V range set by RANGE, and clamp protection to ±16.5 V.
60 V6GND power_in Analog input ground for V6; if a series resistor is used on V6, an equal resistor must be placed on V6GND to avoid offset error.
61 V7 input Single-ended analog input channel 7 with 1 MΩ input impedance, ±10 V or ±5 V range set by RANGE, and clamp protection to ±16.5 V.
62 V7GND power_in Analog input ground for V7; if a series resistor is used on V7, an equal resistor must be placed on V7GND to avoid offset error.
63 V8 input Single-ended analog input channel 8 with 1 MΩ input impedance, ±10 V or ±5 V range set by RANGE, and clamp protection to ±16.5 V.
64 V8GND power_in Analog input ground for V8; if a series resistor is used on V8, an equal resistor must be placed on V8GND to avoid offset error.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LQFP-64(10x10)
Category Data Acquisition
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Signal-to-noise and distortion (SINAD), ±10 V range SINAD 84 84.5 dB 无过采样；±10 V范围 4
Signal-to-noise and distortion (SINAD), ±5 V range SINAD 83.5 84.5 dB 无过采样；±5 V范围 4
Total harmonic distortion (THD) THD -107 -95 dB 4
Differential nonlinearity (DNL) DNL -0.95 0.25 0.95 LSB 4
Integral nonlinearity (INL) INL -0.5 0.25 0.5 LSB 4
Positive/negative full-scale error PFS/NFS -9 2 9 LSB 外部基准电压源 4
Positive/negative full-scale error PFS/NFS -2 2 LSB 内部基准电压源 4
Positive full-scale error drift -2 2 ppm/°C 外部基准电压源 4
Positive full-scale error drift -7 7 ppm/°C 内部基准电压源 4
Negative full-scale error drift -4 4 ppm/°C 外部基准电压源 4
Negative full-scale error drift -8 8 ppm/°C 内部基准电压源 4
Positive/negative full-scale error matching 2 8 LSB ±10 V范围 4
Positive/negative full-scale error matching 4 10 LSB ±5 V范围 4
Bipolar zero-code error -2 0.5 2 LSB ±10 V范围 4
Bipolar zero-code error -3.5 1 3.5 LSB ±5 V范围 4
Bipolar zero-code error matching 1 2.5 LSB ±10 V范围 4
Bipolar zero-code error matching 3 6 LSB ±5 V范围 4
Total unadjusted error (TUE) TUE -0.5 0.5 LSB ±10 V范围 4
Total unadjusted error (TUE) TUE -1 1 LSB ±5 V范围 4
Analog input voltage range VIN -10 10 V RANGE = 1 4
Analog input voltage range VIN -5 5 V RANGE = 0 4
REFIN reference input voltage range VREF 2.475 2.5 2.525 V 5
Reference DC leakage current -1 1 µA 5
Reference output voltage REFIN/REFOUT VREFOUT 2.49 2.505 V 5
Reference voltage temperature coefficient -10 10 ppm/°C 5
Logic output low voltage VOL 0.2 V ISINK = 100 µA 5
Logic input current IIN -2 2 µA 5
Floating-state leakage current -20 1 20 µA 5
Conversion time, all eight channels tCONV 3.45 4 4.15 µs 过采样关闭 6
Analog supply voltage AVCC 4.75 5.25 V 5
Digital interface supply voltage VDRIVE 2.3 5.25 V 5
Total supply current, normal mode (static) ITOTAL 16 22 mA 数字输入 = 0 V或VDRIVE 5
Total supply current, normal mode (operating) ITOTAL 20 27 mA 数字输入 = 0 V或VDRIVE 5
Total supply current, standby mode ITOTAL 5 8 mA 数字输入 = 0 V或VDRIVE 5
Total supply current, shutdown mode ITOTAL 2 6 µA 数字输入 = 0 V或VDRIVE 5
Power dissipation, normal mode (static) 80 115.5 mW 5
Power dissipation, normal mode (operating) 100 142 mW 5
Power dissipation, standby mode 25 42 mW 5
Power dissipation, shutdown mode 10 31.5 µW 5
REGCAP internal regulator output voltage REGCAP 2.5 2.7 V 13
Operating temperature range, B grade TA -40 85 °C B级 10
Parallel/serial read cycle time tCYCLE 5 µs 并行模式，转换期间或之后读取 6
CONVST low pulse width (minimum) t2 25 ns 最短CONVST x低电平脉冲 6
CONVST high pulse width (minimum) t3 25 ns 最短CONVST x高电平脉冲 6
BUSY falling edge to CS falling edge setup time t4 0 ns 6
Maximum allowed delay between CONVST A and CONVST B rising edges t5 0.5 ms CONVST A/CONVST B上升沿之间 6
Last CS rising edge to BUSY falling edge (maximum) t6 25 ns 6
RESET low to CONVST x high delay (minimum) t7 25 ns 6
RD low pulse width t10 16 ns VDRIVE高于4.75 V 6
RD low pulse width t10 21 ns VDRIVE高于3.3 V 6
RD low pulse width t10 25 ns VDRIVE高于2.7 V 6
RD low pulse width t10 32 ns VDRIVE高于2.3 V 6
RD high pulse width t11 15 ns 6
Absolute max: AVCC to AGND AVCC -0.3 7 V AVCC至AGND 10
Absolute max: analog input voltage to AGND VIN -16.5 16.5 V 10
Absolute max: input current to any pin except supplies IIN -10 10 mA 10
Thermal resistance, junction-to-ambient (64-lead LQFP) θJA 45 °C/W 10
Thermal resistance, junction-to-case (64-lead LQFP) θJC 11 °C/W 10

CAD (KiCad official)

  • Symbol: AD7607BSTZ
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: ad7607bstz-etched.step / ad7607bstz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7607bstz.step / ad7607bstz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (32 pp, sha256 bf0c892a0b69e76a, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF