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AD7606C-16BSTZ

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Analog Devices Analog To Digital Converters (ADC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AD7606C-16BSTZ

Analog Devices · Analog To Digital Converters (ADC) · LQFP-64(10x10)

AD7606C-16BSTZ from Analog Devices, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AVCC power_in Analog supply voltage of 4.75 V to 5.25 V feeds the internal front-end amplifiers and ADC core and should be decoupled to AGND.
2 AGND power_in Analog ground reference for all analog circuitry and external reference signals, and all six AGND pins must connect to the system AGND plane.
3 OS0 input Oversampling mode pin that selects the oversampling ratio together with OS1 and OS2, and enables software mode when all three OS pins are tied high.
4 OS1 input Oversampling mode pin that selects the oversampling ratio together with OS0 and OS2, and enables software mode when all three OS pins are tied high.
5 OS2 input Oversampling mode pin that selects the oversampling ratio together with OS0 and OS1, and enables software mode when all three OS pins are tied high.
6 PAR/SER SEL input Interface selection input where logic low selects the parallel interface and logic high selects the serial interface.
7 STBY input Standby mode input that, in hardware mode and combined with RANGE, selects standby or shutdown power-down mode, and is ignored in software mode so it should be tied high.
8 RANGE input Analog input range selection input in hardware mode that must be tied high or low in software mode, and sets the power-down mode when STBY is low.
9 CONVST input Conversion start input whose low-to-high transition samples all eight SAR ADCs, and which can be configured as an external oversampling clock in software mode.
10 WR input Active-low parallel write control for register writes in software mode, with no function in hardware mode so it may be tied high, tied low, or shorted to CONVST.
11 RESET input Active-high reset input where the pulse length selects full or partial reset, and a full reset pulse must be applied after power-up.
12 RD/SCLK input Parallel data read control input (RD) when the parallel interface is selected, or serial clock input (SCLK) when the serial interface is selected.
13 CS input Active-low chip select for ADC data reads and register reads and writes in both the serial and parallel interfaces.
14 BUSY output Busy output that goes high with the CONVST rising edge and remains high until conversion is complete for all channels.
15 FRSTDATA output Output that indicates when the first channel, V1, is being read back on the parallel or serial interface.
16 DB0 bidirectional Parallel data bit 0 three-state input/output that outputs DB0 when CS and RD are low, and must be tied to AGND when using the serial interface.
17 DB1 bidirectional Parallel data bit 1 three-state input/output that outputs DB1 when CS and RD are low, and must be tied to AGND when using the serial interface.
18 DB2 bidirectional Parallel data bit 2 three-state input/output that outputs DB2 when CS and RD are low, and must be tied to AGND when using the serial interface.
19 DB3/DOUTE bidirectional Parallel data bit 3 three-state input/output that outputs DB3 when CS and RD are low, and functions as serial data output DOUTE only in 8 DOUTx mode (otherwise left unconnected).
20 DB4/DOUTF bidirectional Parallel data bit 4 three-state input/output that outputs DB4 when CS and RD are low, and functions as serial data output DOUTF only in 8 DOUTx mode (otherwise left unconnected).
21 DB5/DOUTG bidirectional Parallel data bit 5 three-state input/output that outputs DB5 when CS and RD are low, and functions as serial data output DOUTG only in 8 DOUTx mode (otherwise left unconnected).
22 DB6/DOUTH bidirectional Parallel data bit 6 three-state input/output that outputs DB6 when CS and RD are low, and functions as serial data output DOUTH only in 8 DOUTx mode (otherwise left unconnected).
23 VDRIVE power_in Logic power supply input of 1.71 V to 5.25 V that sets the interface operating voltage, nominally the same as the host DSP or FPGA supply.
24 DB7/DOUTA bidirectional Parallel data bit 7 three-state input/output that outputs DB7 when CS and RD are low, and functions as serial data output DOUTA in serial mode.
25 DB8/DOUTB bidirectional Parallel data bit 8 three-state input/output that outputs DB8 when CS and RD are low, and functions as serial data output DOUTB in serial mode.
26 AGND power_in Analog ground reference for all analog circuitry, and must connect to the system AGND plane.
27 DB9/DOUTC bidirectional Parallel data bit 9 three-state input/output that outputs DB9 when CS and RD are low, and functions as serial data output DOUTC in software mode with the 4 or 8 DOUTx option.
28 DB10/DOUTD bidirectional Parallel data bit 10 three-state input/output that outputs DB10 when CS and RD are low, and functions as serial data output DOUTD in software mode with the 4 or 8 DOUTx option.
29 DB11/SDI bidirectional Parallel data bit 11 three-state input/output that outputs DB11 when CS and RD are low, and functions as serial data input SDI in software mode with the serial interface.
30 DB12 bidirectional Parallel data bit 12 three-state input/output that outputs DB12 when CS and RD are low, and must be tied to AGND when using the serial interface.
31 DB13 bidirectional Parallel data bit 13 three-state input/output that outputs DB13 when CS and RD are low, and must be tied to AGND when using the serial interface.
32 DB14 bidirectional Parallel data bit 14 three-state input/output that outputs DB14 when CS and RD are low, and must be tied to AGND when using the serial interface.
33 DB15 bidirectional Parallel data bit 15 three-state input/output that outputs DB15 when CS and RD are low, and must be tied to AGND when using the serial interface.
34 REF SELECT input Internal or external reference selection where logic high enables the internal 2.5 V reference and logic low disables it and requires an external 2.5 V reference on REFIN.
35 AGND power_in Analog ground reference for all analog circuitry, and must connect to the system AGND plane.
36 REGCAP power_out Decoupling pin for the 1.9 V internal regulator output (ALDO and DLDO), which must be decoupled to AGND with a separate 1 µF capacitor and sits at 1.875 V to 1.93 V.
37 AVCC power_in Analog supply voltage of 4.75 V to 5.25 V feeding the internal front-end amplifiers and ADC core, to be decoupled to AGND.
38 AVCC power_in Analog supply voltage of 4.75 V to 5.25 V feeding the internal front-end amplifiers and ADC core, to be decoupled to AGND.
39 REGCAP power_out Decoupling pin for the 1.9 V internal regulator output (ALDO and DLDO), which must be decoupled to AGND with a separate 1 µF capacitor and sits at 1.875 V to 1.93 V.
40 AGND power_in Analog ground reference for all analog circuitry, and must connect to the system AGND plane.
41 AGND power_in Analog ground reference for all analog circuitry, and must connect to the system AGND plane.
42 REFIN/REFOUT bidirectional Reference output providing the internal 2.5 V reference when REF SELECT is high, or reference input accepting an external 2.5 V when REF SELECT is low, with a 100 nF capacitor to ground close to REFGND.
43 REFGND power_in Reference ground pin that must be connected to AGND.
44 REFCAPA power_out Reference buffer output force and sense pin that must be connected to REFCAPB and decoupled to AGND with a low-ESR 10 µF ceramic capacitor, typically 4.4 V.
45 REFCAPB power_out Reference buffer output force and sense pin that must be connected to REFCAPA and decoupled to AGND with a low-ESR 10 µF ceramic capacitor, typically 4.4 V.
46 REFGND power_in Reference ground pin that must be connected to AGND.
47 AGND power_in Analog ground reference for all analog circuitry, and must connect to the system AGND plane.
48 AVCC power_in Analog supply voltage of 4.75 V to 5.25 V feeding the internal front-end amplifiers and ADC core, to be decoupled to AGND.
49 V1+ passive Channel 1 positive analog input pin, whose input clamp protection tolerates voltages up to ±21 V.
50 V1- passive Channel 1 negative analog input pin, whose input clamp protection tolerates voltages up to ±21 V.
51 V2+ passive Channel 2 positive analog input pin, whose input clamp protection tolerates voltages up to ±21 V.
52 V2- passive Channel 2 negative analog input pin, whose input clamp protection tolerates voltages up to ±21 V.
53 V3+ passive Channel 3 positive analog input pin, whose input clamp protection tolerates voltages up to ±21 V.
54 V3- passive Channel 3 negative analog input pin, whose input clamp protection tolerates voltages up to ±21 V.
55 V4+ passive Channel 4 positive analog input pin, whose input clamp protection tolerates voltages up to ±21 V.
56 V4- passive Channel 4 negative analog input pin, whose input clamp protection tolerates voltages up to ±21 V.
57 V5+ passive Channel 5 positive analog input pin, whose input clamp protection tolerates voltages up to ±21 V.
58 V5- passive Channel 5 negative analog input pin, whose input clamp protection tolerates voltages up to ±21 V.
59 V6+ passive Channel 6 positive analog input pin, whose input clamp protection tolerates voltages up to ±21 V.
60 V6- passive Channel 6 negative analog input pin, whose input clamp protection tolerates voltages up to ±21 V.
61 V7+ passive Channel 7 positive analog input pin, whose input clamp protection tolerates voltages up to ±21 V.
62 V7- passive Channel 7 negative analog input pin, whose input clamp protection tolerates voltages up to ±21 V.
63 V8+ passive Channel 8 positive analog input pin, whose input clamp protection tolerates voltages up to ±21 V.
64 V8- passive Channel 8 negative analog input pin, whose input clamp protection tolerates voltages up to ±21 V.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LQFP-64(10x10)
Category Data Acquisition
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Differential Nonlinearity (DNL) DNL -0.99 0.5 0.99 LSB 7
Integral Nonlinearity (INL), bipolar input ranges INL -2 0.5 2 LSB Bipolar input ranges 7
Integral Nonlinearity (INL), unipolar input ranges INL -1 1 LSB Unipolar input ranges 7
Total Unadjusted Error (TUE), external reference, bipolar input ranges TUE -30 6 30 LSB External reference, bipolar input ranges 7
Total Unadjusted Error (TUE), external reference, ±2.5 V range TUE -45 6 45 LSB External reference, ±2.5 V range 7
Total Unadjusted Error (TUE), unipolar input ranges TUE -70 15 70 LSB Unipolar input ranges 7
Positive and Negative Full-Scale (FS) Error, bipolar ranges -30 5 30 LSB Bipolar ranges 7
Positive and Negative FS Error Drift -3 0.5 3 ppm/°C 7
Positive and Negative FS Error Matching 4 20 LSB 7
Bipolar Zero Code Error, 2.5 V range -40 2 40 LSB 2.5 V range 7
Bipolar Zero Code Error, all other input ranges -20 2 20 LSB All other input ranges 7
Bipolar Zero Code Error Drift, 2.5 V range -5 2 5 ppm/°C 2.5 V range 7
Bipolar Zero Code Error Drift, all other input ranges -2.5 0.5 2.5 ppm/°C All other input ranges 7
Bipolar Zero Code Error Matching 5 25 LSB 7
Full-Scale (FS) Error, unipolar ranges -60 15 60 LSB Unipolar ranges 7
FS Error Drift, unipolar ranges -7 1 7 ppm/°C Unipolar ranges 7
FS Error Matching, unipolar ranges 5 40 LSB Unipolar ranges 7
Zero Scale Error, unipolar ranges -50 15 50 LSB Unipolar ranges 7
Zero Scale Error Drift, unipolar ranges -7 2.5 7 ppm/°C Unipolar ranges 7
Zero Scale Error Matching, unipolar ranges 5 40 LSB Unipolar ranges 7
Series resistor range for PFS and NFS calibration 1 64 kΩ Series resistor in front of the Vx+ and Vx− inputs 7
Offset Calibration Range -128 127 LSB 7
Phase Calibration Range 1 255 μs 7
PFS and NFS Error after gain calibration -15 15 LSB After gain calibration 7
Input Voltage Range, ±20 V bipolar differential VIN -20 20 V VIN = Vx+ − Vx− 7
Input Voltage Range, ±12.5 V bipolar differential VIN -12.5 12.5 V VIN = Vx+ − Vx− 7
Input Voltage Range, ±10 V bipolar differential VIN -10 10 V VIN = Vx+ − Vx− 7
Input Voltage Range, ±5 V bipolar differential VIN -5 5 V VIN = Vx+ − Vx− 7
Input Voltage Range, ±12.5 V bipolar single-ended VIN -12.5 12.5 V Bipolar single-ended range 7
Input Voltage Range, ±10 V bipolar single-ended VIN -10 10 V Bipolar single-ended range 7
Input Voltage Range, ±6.25 V bipolar single-ended VIN -6.25 6.25 V Bipolar single-ended range 8
Input Voltage Range, ±5 V bipolar single-ended VIN -5 5 V Bipolar single-ended range 8
Input Voltage Range, ±2.5 V bipolar single-ended VIN -2.5 2.5 V Bipolar single-ended range 8
Input Voltage Range, 0 V to 12.5 V unipolar single-ended VIN 0 12.5 V Unipolar single-ended range 8
Input Voltage Range, 0 V to 10 V unipolar single-ended VIN 0 10 V Unipolar single-ended range 8
Input Voltage Range, 0 V to 5 V unipolar single-ended VIN 0 5 V Unipolar single-ended range 8
Common-Mode Input Range, ±20 V bipolar differential range -10 10 V ±20 V bipolar differential range 8
Common-Mode Input Range, ±12.5 V bipolar differential range -7.8 7.8 V ±12.5 V bipolar differential range 8
Common-Mode Input Range, ±10 V bipolar differential range -6 7 V ±10 V bipolar differential range 8
Common-Mode Input Range, ±5 V bipolar differential range -3 5 V ±5 V bipolar differential range 8
Input Impedance (RIN) RIN 1 1.2 MΩ 8
Reference Input Voltage, external reference 2.495 2.5 2.505 V External reference 8
Reference Output Voltage, internal reference 2.4975 2.5 2.5025 V Internal reference, TA = 25°C 8
Reference Temperature Coefficient -10 3 10 ppm/°C 8
Reference Voltage to the ADC (REFCAPA, REFCAPB) 4.39 4.41 V REFCAPA (Pin 44) and REFCAPB (Pin 45) 8
Input Current (IIN) IIN -1 1 µA 8
Output Low Voltage (VOL) VOL 0.2 V Current sink (ISINK) = 100 µA 8
AVCC supply voltage AVCC 4.75 5 5.25 V 8
VDRIVE supply voltage VDRIVE 1.71 5.25 V 8
AVCC to AGND AVCC -0.3 6.5 V TA = 25°C, unless otherwise noted 14
Analog Input Voltage to AGND -21 21 V TA = 25°C, unless otherwise noted 14
Input Current to Any Pin Except Supplies -10 10 mA TA = 25°C, unless otherwise noted 14
Operating Temperature Range TA -40 125 °C 14
Storage Temperature Range -65 150 °C 14
Junction Temperature TJ 150 °C 14
Pb-Free Temperature, Soldering Reflow 260 °C Pb-free soldering reflow 14
Thermal resistance, junction to ambient (ST-64-2) θJA 40 °C/W Simulated JEDEC 2s2p PCB, natural convection 14
Thermal resistance, junction to case (ST-64-2) θJC 7 °C/W 14

CAD (KiCad official)

  • Symbol: AD7606C-16BSTZ
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: ad7606c-16bstz-etched.step / ad7606c-16bstz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7606c-16bstz.step / ad7606c-16bstz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (80 pp, sha256 51b7051688a3c9ec, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF