component
AD7321BRUZ-REEL7
Public Made by Adomby adom
Analog Devices Digital To Analog Converters (DACs), TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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"digikey": "AD7321BRUZ-REEL7TR-ND",
"mouser": "584-AD7321BRUZ-R7"
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"name": "CS",
"type": "input",
"description": "Active-low chip select that initiates conversions on the AD7321 and frames the serial data transfer."
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{
"number": "2",
"name": "DIN",
"type": "input",
"description": "Data input for writing on-chip registers, clocked in on the falling edge of SCLK."
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{
"number": "3",
"name": "DGND",
"type": "power_in",
"description": "Digital ground reference for all digital circuitry; must not be more than 0.3 V from AGND, even transiently."
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{
"number": "4",
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"type": "power_in",
"description": "Analog ground reference for all analog circuitry; analog inputs and external reference are referred to this pin and must not be more than 0.3 V from DGND."
},
{
"number": "5",
"name": "REFIN/OUT",
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{
"number": "6",
"name": "VSS",
"type": "power_in",
"description": "Negative analog supply for the analog input section, specified as −12 V to −16.5 V in the Specifications table."
},
{
"number": "7",
"name": "VIN0",
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"description": "Analog input channel 0, multiplexed into the on-chip track-and-hold; configurable as single-ended, true differential pair, or pseudo differential, with input range set in the range register."
},
{
"number": "8",
"name": "VIN1",
"type": "input",
"description": "Analog input channel 1, multiplexed into the on-chip track-and-hold; configurable as single-ended, true differential pair, or pseudo differential, with input range set in the range register."
},
{
"number": "9",
"name": "VDD",
"type": "power_in",
"description": "Positive analog supply for the analog input section, specified as 12 V to 16.5 V in the Specifications table."
},
{
"number": "10",
"name": "VCC",
"type": "power_in",
"description": "Analog supply for the ADC core, 2.7 V to 5.25 V, to be decoupled to AGND."
},
{
"number": "11",
"name": "VDRIVE",
"type": "power_in",
"description": "Logic supply that sets the digital interface voltage (2.7 V to 5.25 V); decouple to DGND and do not exceed VCC by more than 0.3 V."
},
{
"number": "12",
"name": "DOUT",
"type": "output",
"description": "Serial data output; bits clock out on the falling edge of SCLK, with 16 SCLKs needed to read data MSB first."
},
{
"number": "13",
"name": "DGND",
"type": "power_in",
"description": "Digital ground reference for all digital circuitry; same requirement as pin 3, must not be more than 0.3 V from AGND."
},
{
"number": "14",
"name": "SCLK",
"type": "input",
"description": "Serial clock input used both for accessing data and as the conversion clock source."
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"Package": "TSSOP-14",
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"conditions": "See Table 6",
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{
"name": "VSS supply voltage",
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"conditions": "See Table 6",
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{
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"name": "VDRIVE to AGND, DGND",
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{
"name": "AGND to DGND",
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{
"name": "Digital input voltage to DGND",
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{
"name": "Input current to any pin except supplies",
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{
"name": "Operating temperature range",
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{
"name": "Storage temperature range",
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{
"name": "Junction temperature",
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"conditions": "VCC < 4.75 V; VCC = 4.75 V to 5.25 V",
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{
"name": "fSCLK serial clock frequency (max)",
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{
"name": "Minimum time between end of serial read and next falling edge of CS",
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{
"name": "Minimum time between end of serial read and next falling edge of CS",
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"source": "datasheet"
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{
"name": "Minimum CS pulse width",
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{
"name": "Minimum CS pulse width",
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"conditions": "VCC = 4.75 V to 5.25 V",
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{
"name": "CS to SCLK set-up time, bipolar input ranges",
"symbol": "t2",
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"conditions": "Bipolar input ranges (±10 V, ±5 V, ±2.5 V); VCC < 4.75 V",
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{
"name": "CS to SCLK set-up time, bipolar input ranges",
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"conditions": "Bipolar input ranges (±10 V, ±5 V, ±2.5 V); VCC = 4.75 V to 5.25 V",
"source_page": 7,
"source": "datasheet"
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{
"name": "Delay from CS until DOUT three-state disabled",
"symbol": "t3",
"kind": "timing",
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"min": null,
"typ": null,
"max": 26,
"conditions": "VCC < 4.75 V",
"source_page": 7,
"source": "datasheet"
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{
"name": "Delay from CS until DOUT three-state disabled",
"symbol": "t3",
"kind": "timing",
"unit": "ns",
"min": null,
"typ": null,
"max": 14,
"conditions": "VCC = 4.75 V to 5.25 V",
"source_page": 7,
"source": "datasheet"
},
{
"name": "Data access time after SCLK falling edge",
"symbol": "t4",
"kind": "timing",
"unit": "ns",
"min": null,
"typ": null,
"max": 57,
"conditions": "VCC < 4.75 V",
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"source": "datasheet"
},
{
"name": "Data access time after SCLK falling edge",
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"typ": null,
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"conditions": "VCC = 4.75 V to 5.25 V",
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"source": "datasheet"
},
{
"name": "SCLK to data valid hold time",
"symbol": "t7",
"kind": "timing",
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"min": 13,
"typ": null,
"max": null,
"conditions": "VCC < 4.75 V",
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{
"name": "SCLK to data valid hold time",
"symbol": "t7",
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"min": 8,
"typ": null,
"max": null,
"conditions": "VCC = 4.75 V to 5.25 V",
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{
"name": "SCLK falling edge to DOUT high impedance",
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"kind": "timing",
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"min": null,
"typ": null,
"max": 40,
"conditions": "VCC < 4.75 V",
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{
"name": "SCLK falling edge to DOUT high impedance",
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"kind": "timing",
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"min": null,
"typ": null,
"max": 22,
"conditions": "VCC = 4.75 V to 5.25 V",
"source_page": 7,
"source": "datasheet"
},
{
"name": "DIN set-up time prior to SCLK falling edge",
"symbol": "t9",
"kind": "timing",
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"min": 4,
"typ": null,
"max": null,
"conditions": "VCC < 4.75 V; VCC = 4.75 V to 5.25 V",
"source_page": 7,
"source": "datasheet"
},
{
"name": "DIN hold time after SCLK falling edge",
"symbol": "t10",
"kind": "timing",
"unit": "ns",
"min": 2,
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"conditions": "VCC < 4.75 V; VCC = 4.75 V to 5.25 V",
"source_page": 7,
"source": "datasheet"
},
{
"name": "Power-up from autostandby",
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"kind": "timing",
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"conditions": "VCC < 4.75 V; VCC = 4.75 V to 5.25 V",
"source_page": 7,
"source": "datasheet"
},
{
"name": "Power-up from full shutdown/autoshutdown mode, internal reference",
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"conditions": "VCC < 4.75 V; VCC = 4.75 V to 5.25 V",
"source_page": 7,
"source": "datasheet"
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{
"name": "Offset error, differential mode",
"symbol": "",
"kind": "electrical",
"unit": "%FSR",
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"conditions": "Differential mode, LSB = FSR/8192; equates to −7/+10 LSBs",
"source_page": 4,
"source": "datasheet"
},
{
"name": "Gain error, differential mode",
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{
"name": "Integral nonlinearity, differential mode",
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