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AD7321BRUZ-REEL7
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Analog Devices Digital To Analog Converters (DACs), TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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AD7321BRUZ-REEL7
Analog Devices · Digital To Analog Converters (DACs) · TSSOP-14
AD7321BRUZ-REEL7 from Analog Devices, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS | input | Active-low chip select that initiates conversions on the AD7321 and frames the serial data transfer. |
| 2 | DIN | input | Data input for writing on-chip registers, clocked in on the falling edge of SCLK. |
| 3 | DGND | power_in | Digital ground reference for all digital circuitry; must not be more than 0.3 V from AGND, even transiently. |
| 4 | AGND | power_in | Analog ground reference for all analog circuitry; analog inputs and external reference are referred to this pin and must not be more than 0.3 V from DGND. |
| 5 | REFIN/OUT | passive | Reference input/output: outputs the nominal 2.5 V internal reference, which requires a 680 nF capacitor, or accepts an external reference (external mode is the power-up default). |
| 6 | VSS | power_in | Negative analog supply for the analog input section, specified as −12 V to −16.5 V in the Specifications table. |
| 7 | VIN0 | input | Analog input channel 0, multiplexed into the on-chip track-and-hold; configurable as single-ended, true differential pair, or pseudo differential, with input range set in the range register. |
| 8 | VIN1 | input | Analog input channel 1, multiplexed into the on-chip track-and-hold; configurable as single-ended, true differential pair, or pseudo differential, with input range set in the range register. |
| 9 | VDD | power_in | Positive analog supply for the analog input section, specified as 12 V to 16.5 V in the Specifications table. |
| 10 | VCC | power_in | Analog supply for the ADC core, 2.7 V to 5.25 V, to be decoupled to AGND. |
| 11 | VDRIVE | power_in | Logic supply that sets the digital interface voltage (2.7 V to 5.25 V); decouple to DGND and do not exceed VCC by more than 0.3 V. |
| 12 | DOUT | output | Serial data output; bits clock out on the falling edge of SCLK, with 16 SCLKs needed to read data MSB first. |
| 13 | DGND | power_in | Digital ground reference for all digital circuitry; same requirement as pin 3, must not be more than 0.3 V from AGND. |
| 14 | SCLK | input | Serial clock input used both for accessing data and as the conversion clock source. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSSOP-14 |
| Category | Data Converters |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD supply voltage | VDD | 12 | 16.5 | V | See Table 6 | 6 | |
| VSS supply voltage | VSS | -16.5 | -12 | V | See Table 6 | 6 | |
| VCC analog supply voltage | VCC | 2.7 | 5.25 | V | See Table 6 | 6 | |
| VDRIVE logic supply voltage | VDRIVE | 2.7 | 5.25 | V | 6 | ||
| Reference input voltage range | 2.5 | 3 | V | 5 | |||
| VDD to AGND, DGND | -0.3 | 16.5 | V | 8 | |||
| VSS to AGND, DGND | -16.5 | 0.3 | V | 8 | |||
| VCC to AGND, DGND | -0.3 | 7 | V | 8 | |||
| VDRIVE to AGND, DGND | -0.3 | 7 | V | 8 | |||
| AGND to DGND | -0.3 | 0.3 | V | 8 | |||
| Digital input voltage to DGND | -0.3 | 7 | V | 8 | |||
| Input current to any pin except supplies | -10 | 10 | mA | 8 | |||
| Operating temperature range | -40 | 85 | °C | 8 | |||
| Storage temperature range | -65 | 150 | °C | 8 | |||
| Junction temperature | 150 | °C | 8 | ||||
| fSCLK serial clock frequency (min) | fSCLK | 50 | kHz | VCC < 4.75 V; VCC = 4.75 V to 5.25 V | 7 | ||
| fSCLK serial clock frequency (max) | fSCLK | 10 | MHz | VCC < 4.75 V; VCC = 4.75 V to 5.25 V | 7 | ||
| Minimum time between end of serial read and next falling edge of CS | tQUIET | 75 | ns | VCC < 4.75 V | 7 | ||
| Minimum time between end of serial read and next falling edge of CS | tQUIET | 60 | ns | VCC = 4.75 V to 5.25 V | 7 | ||
| Minimum CS pulse width | t1 | 12 | ns | VCC < 4.75 V | 7 | ||
| Minimum CS pulse width | t1 | 5 | ns | VCC = 4.75 V to 5.25 V | 7 | ||
| CS to SCLK set-up time, bipolar input ranges | t2 | 25 | ns | Bipolar input ranges (±10 V, ±5 V, ±2.5 V); VCC < 4.75 V | 7 | ||
| CS to SCLK set-up time, bipolar input ranges | t2 | 20 | ns | Bipolar input ranges (±10 V, ±5 V, ±2.5 V); VCC = 4.75 V to 5.25 V | 7 | ||
| Delay from CS until DOUT three-state disabled | t3 | 26 | ns | VCC < 4.75 V | 7 | ||
| Delay from CS until DOUT three-state disabled | t3 | 14 | ns | VCC = 4.75 V to 5.25 V | 7 | ||
| Data access time after SCLK falling edge | t4 | 57 | ns | VCC < 4.75 V | 7 | ||
| Data access time after SCLK falling edge | t4 | 43 | ns | VCC = 4.75 V to 5.25 V | 7 | ||
| SCLK to data valid hold time | t7 | 13 | ns | VCC < 4.75 V | 7 | ||
| SCLK to data valid hold time | t7 | 8 | ns | VCC = 4.75 V to 5.25 V | 7 | ||
| SCLK falling edge to DOUT high impedance | t8 | 40 | ns | VCC < 4.75 V | 7 | ||
| SCLK falling edge to DOUT high impedance | t8 | 22 | ns | VCC = 4.75 V to 5.25 V | 7 | ||
| DIN set-up time prior to SCLK falling edge | t9 | 4 | ns | VCC < 4.75 V; VCC = 4.75 V to 5.25 V | 7 | ||
| DIN hold time after SCLK falling edge | t10 | 2 | ns | VCC < 4.75 V; VCC = 4.75 V to 5.25 V | 7 | ||
| Power-up from autostandby | tPOWER-UP | 750 | ns | VCC < 4.75 V; VCC = 4.75 V to 5.25 V | 7 | ||
| Power-up from full shutdown/autoshutdown mode, internal reference | tPOWER-UP | 500 | µs | VCC < 4.75 V; VCC = 4.75 V to 5.25 V | 7 | ||
| Offset error, differential mode | -0.085 | 0.122 | %FSR | Differential mode, LSB = FSR/8192; equates to −7/+10 LSBs | 4 | ||
| Gain error, differential mode | -0.171 | 0.171 | %FSR | Differential mode, LSB = FSR/8192; equates to ±14 LSBs | 4 | ||
| Integral nonlinearity, differential mode | -1.1 | 1.1 | LSB | Differential mode; VCC = 3 V to 5.25 V, typ for VCC = 2.7 V | 4 | ||
| Differential nonlinearity, differential mode | -0.9 | 1.2 | LSB | Differential mode; guaranteed no missing codes to 13 bits | 4 | ||
| Integral nonlinearity, single-ended/pseudo differential mode | -1 | 1 | LSB | Single-ended/pseudo differential mode, VCC = 3 V to 5.25 V, typ for VCC = 2.7 V | 4 | ||
| Offset error, single-ended/pseudo differential mode | -0.098 | 0.22 | %FSR | Single-ended/pseudo differential mode, LSB = FSR/4096; equates to −4/+9 LSBs | 4 | ||
| Gain error, single-ended/pseudo differential mode | -0.195 | 0.195 | %FSR | Single-ended/pseudo differential mode, LSB = FSR/4096; equates to ±8 LSBs | 4 | ||
| Input low voltage, VINL | VINL | 0.8 | V | VCC = 4.75 V to 5.25 V | 5 | ||
| Input low voltage, VINL | VINL | 0.4 | V | VCC = 2.7 V to 3.6 V | 5 | ||
| Input high voltage, VINH | VINH | 2.4 | V | 5 | |||
| Output low voltage, VOL | VOL | 0.4 | V | ISINK = 200 µA | 5 | ||
| Input current, IIN | IIN | -1 | 1 | µA | VIN = 0 V or VDRIVE | 5 | |
| Floating-state leakage current | -1 | 1 | µA | 5 | |||
| DC leakage current, analog input | -80 | 80 | nA | VIN = VDD or VSS | 5 | ||
| Reference output voltage error at 25°C | -5 | 5 | mV | 5 | |||
| Reference output voltage error TMIN to TMAX | -10 | 10 | mV | 5 | |||
| Input DC leakage current, REFIN/OUT | -1 | 1 | µA | 5 | |||
| Thermal impedance, junction to ambient (TSSOP) | θJA | 113.5 | °C/W | TSSOP package | 8 | ||
| Thermal impedance, junction to case (TSSOP) | θJC | 30 | °C/W | TSSOP package | 8 | ||
| Normal mode (operational) IDD supply current | IDD | 180 | µA | VDD = 16.5 V | 6 | ||
| Normal mode (operational) ISS supply current | ISS | 205 | µA | VSS = −16.5 V | 6 | ||
| Normal mode (operational) ICC and IDRIVE supply current | ICC and IDRIVE | 2.2 | mA | VCC/VDRIVE = 5.25 V | 6 | ||
| Normal mode (operational) power dissipation | 18 | mW | VDD = 16.5 V, VSS = −16.5 V, VCC = 5.25 V | 6 | |||
| Reference output voltage | 2.5 | V | 5 | ||||
| Power-up from full shutdown/autoshutdown mode, external reference | tPOWER-UP | 25 | µs | VCC < 4.75 V; VCC = 4.75 V to 5.25 V | 7 |
CAD (KiCad official)
- Symbol:
AD7321BRUZ-REEL7 - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
ad7321bruz-reel7-etched.step/ad7321bruz-reel7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad7321bruz-reel7.step/ad7321bruz-reel7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (36 pp, sha256
f4b044579f20507d, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).