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AD7266BCPZ-REEL7

Analog Devices · Analog To Digital Converters (ADC) · LFCSP-32(5x5)

AD7266BCPZ-REEL7 from Analog Devices, in a LFCSP-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	DGND	power_in	Digital ground reference for all digital circuitry; both DGND pins must connect to the system DGND plane and must not be more than 0.3 V from AGND, even transiently.
2	REF SELECT	input	Logic input selecting the reference: tied to DGND uses the on-chip 2.5 V reference with DCAPA and DCAPB decoupled, while a logic high allows an external reference through DCAPA and/or DCAPB.
3	AVDD	power_in	Analog supply voltage of 2.7 V to 5.25 V, which must stay within 0.3 V of DVDD even transiently and be decoupled to AGND.
4	DCAPA	passive	Decoupling capacitor pin for the ADC A reference buffer, with 470 nF recommended; the external reference range depends on the selected analog input range.
5	AGND	power_in	Analog ground reference for all analog circuitry, with all three AGND pins connected to the AGND plane and not more than 0.3 V from DGND, even transiently.
6	AGND	power_in	Analog ground reference for all analog circuitry, with all three AGND pins connected to the AGND plane and not more than 0.3 V from DGND, even transiently.
7	VA1	input	Analog input of ADC A, programmable as one of six single-ended channels or three true differential pairs.
8	VA2	input	Analog input of ADC A, programmable as one of six single-ended channels or three true differential pairs.
9	VA3	input	Analog input of ADC A, programmable as one of six single-ended channels or three true differential pairs.
10	VA4	input	Analog input of ADC A, programmable as one of six single-ended channels or three true differential pairs.
11	VA5	input	Analog input of ADC A, programmable as one of six single-ended channels or three true differential pairs.
12	VA6	input	Analog input of ADC A, programmable as one of six single-ended channels or three true differential pairs.
13	VB6	input	Analog input of ADC B, programmable as one of six single-ended channels or three true differential pairs.
14	VB5	input	Analog input of ADC B, programmable as one of six single-ended channels or three true differential pairs.
15	VB4	input	Analog input of ADC B, programmable as one of six single-ended channels or three true differential pairs.
16	VB3	input	Analog input of ADC B, programmable as one of six single-ended channels or three true differential pairs.
17	VB2	input	Analog input of ADC B, programmable as one of six single-ended channels or three true differential pairs.
18	VB1	input	Analog input of ADC B, programmable as one of six single-ended channels or three true differential pairs.
19	AGND	power_in	Analog ground reference for all analog circuitry, with all three AGND pins connected to the AGND plane and not more than 0.3 V from DGND, even transiently.
20	DCAPB	passive	Decoupling capacitor pin for the ADC B reference buffer, with 470 nF recommended; the external reference range depends on the selected analog input range.
21	RANGE	input	Logic input setting the analog input range: logic low gives 0 V to VREF, and logic high when CS goes low gives 2 × VREF.
22	SGL/DIFF	input	Logic input selecting the input configuration: logic low selects differential operation and logic high selects single-ended operation.
23	A2	input	Multiplexer select logic input choosing the channel pair converted simultaneously, which must be set before the acquisition time and the falling edge of CS.
24	A1	input	Multiplexer select logic input choosing the channel pair converted simultaneously, which must be set before the acquisition time and the falling edge of CS.
25	A0	input	Multiplexer select logic input choosing the channel pair converted simultaneously, which must be set before the acquisition time and the falling edge of CS.
26	CS	input	Active-low chip select that initiates conversions on the AD7266 and frames the serial data transfer.
27	SCLK	input	Serial clock logic input that clocks data out of the AD7266 and is also the clock source for the conversion process.
28	DOUTB	output	Serial data output for ADC B, MSB first with two leading zeros, requiring 14 SCLKs to access the data, and clocked out on the SCLK falling edge.
29	DGND	power_in	Digital ground reference for all digital circuitry; both DGND pins must connect to the system DGND plane and must not be more than 0.3 V from AGND, even transiently.
30	DOUTA	output	Serial data output for ADC A, MSB first with two leading zeros, requiring 14 SCLKs to access the data, and clocked out on the SCLK falling edge.
31	VDRIVE	power_in	Logic interface supply that sets the digital interface voltage, which must be decoupled to DGND and must not exceed DVDD or AVDD by more than 0.3 V.
32	DVDD	power_in	Digital supply voltage of 2.7 V to 5.25 V, which must stay within 0.3 V of AVDD even transiently and be decoupled to DGND.
33	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	LFCSP-32(5x5)
Category	Data Acquisition
Pins	33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Signal-to-Noise Ratio (SNR), differential mode	SNR	71			dB	fIN = 50 kHz sine wave; differential mode	3
Signal-to-Noise Ratio (SNR), single-ended and pseudo differential modes	SNR	69			dB	fIN = 50 kHz sine wave; single-ended and pseudo differential modes	3
Signal-to-Noise + Distortion Ratio (SINAD), differential mode	SINAD	70			dB	fIN = 50 kHz sine wave; differential mode	3
Signal-to-Noise + Distortion Ratio (SINAD), single-ended and pseudo differential modes	SINAD	68			dB	fIN = 50 kHz sine wave; single-ended and pseudo differential modes	3
Total Harmonic Distortion (THD), differential mode	THD			-77	dB	fIN = 50 kHz sine wave; differential mode	3
Total Harmonic Distortion (THD), single-ended and pseudo differential modes	THD			-73	dB	fIN = 50 kHz sine wave; single-ended and pseudo differential modes	3
Spurious-Free Dynamic Range (SFDR)	SFDR			-75	dB	fIN = 50 kHz sine wave	3
Aperture Delay				11	ns		3
Integral Nonlinearity (INL), differential mode	INL	-1	0.5	1	LSB	differential mode	3
Integral Nonlinearity (INL), single-ended and pseudo differential modes	INL	-1.5	0.5	1.5	LSB	single-ended and pseudo differential modes	3
Differential Nonlinearity (DNL), differential mode	DNL	-0.99		0.99	LSB	Differential mode	3
Differential Nonlinearity (DNL), single-ended and pseudo differential modes	DNL	-0.99		1.5	LSB	Single-ended and pseudo differential modes	3
Offset Error (straight binary output coding)		-7	2	7	LSB	Straight binary output coding	3
Gain Error (straight binary output coding)		-2.5		2.5	LSB	Straight binary output coding	3
Positive Gain Error (twos complement output coding)		-2		2	LSB	Twos complement output coding	3
Zero Code Error (twos complement output coding)		-5		5	LSB	Twos complement output coding	3
Negative Gain Error (twos complement output coding)		-2		2	LSB	Twos complement output coding	3
DC Leakage Current (analog input)		-1		1	μA		4
Reference Output Voltage		2.5		2.5	V		4
Reference Output Voltage tolerance		-0.2		0.2	%	@ 25°C	4
Reference Input Voltage Range		0.1			V	See Typical Performance Characteristics section	4
DC Leakage Current (external reference applied to DCAPA/DCAPB)		-2		2	μA	External reference applied to Pin DCAPA/Pin DCAPB	4
Reference Temperature Coefficient			10	20	ppm/°C		4
Input High Voltage	VINH	2.8			V		4
Input Low Voltage	VINL			0.4	V		4
Output Low Voltage	VOL			0.4	V		4
Track-and-Hold Acquisition Time				90	ns	Full-scale step input; VDD = 5 V	4
Track-and-Hold Acquisition Time				110	ns	Full-scale step input; VDD = 3 V	4
Throughput Rate				2	MSPS		4
VDD supply voltage	VDD	2.7		5.25	V		4
VDRIVE supply voltage	VDRIVE	2.7		5.25	V		4
IDD Normal Mode (Static)	IDD			2.3	mA	VDD = 5.25 V	4
IDD Operational, fS = 2 MSPS	IDD		5.7	6.4	mA	VDD = 5.25 V	4
IDD Operational, fS = 1.5 MSPS	IDD		3.4	4	mA	VDD = 3.6 V	4
IDD Partial Power-Down Mode	IDD			500	μA	Static	4
IDD Full Power-Down Mode (VDD)	IDD			1	μA	TA = −40°C to +85°C	4
IDD Full Power-Down Mode (VDD)	IDD			2.8	μA	TA > 85°C to 125°C	4
Power Dissipation, Normal Mode (Operational)				33.6	mW	VDD = 5.25 V	4
Absolute maximum VDD to AGND		-0.3		7	V		6
Absolute maximum DVDD to DGND		-0.3		7	V		6
Absolute maximum AVDD to DVDD		-0.3		0.3	V		6
Absolute maximum AGND to DGND		-0.3		0.3	V		6
Absolute maximum input current to any pin except supplies		-10		10	mA		6
Absolute maximum digital input voltage to DGND		-0.3		7	V		6
Operating Temperature Range		-40		125	°C		6
Storage Temperature Range		-65		150	°C		6
Junction Temperature				150	°C		6
Reflow Temperature				255	°C	10 to 30 sec	6
ESD				1.5	kV		6
Thermal impedance junction-to-ambient (LFCSP)	θJA		108.2		°C/W	LFCSP	6
Thermal impedance junction-to-case (LFCSP)	θJC		32.71		°C/W	LFCSP	6
fSCLK	fSCLK	1			MHz	TA = −40°C to +85°C	5
fSCLK	fSCLK			32	MHz		5
tCONVERT	tCONVERT			437.5	ns	fSCLK = 32 MHz, VDD = 5 V, fSAMPLE = 2 MSPS	5
tQUIET	tQUIET	30			ns	Minimum time between end of serial read and next falling edge of CS	5
t2 CS to SCLK setup time	t2	15			ns	VDD = 5 V; TA = −40°C to +85°C	5
t3 Delay from CS until DOUTA and DOUTB three-state disabled	t3			15	ns		5
t4 Data access time after SCLK falling edge	t4			27	ns	VDD = 5 V	5
t4 Data access time after SCLK falling edge	t4			36	ns	VDD = 3 V	5
t8 CS rising edge to DOUTA, DOUTB high impedance	t8			15	ns		5

CAD (KiCad official)

Symbol: AD7266BCPZ-REEL7
Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
3D model: LFCSP-32(5x5) (KiCad packages3D, STEP)
3D model files: ad7266bcpz-reel7-etched.step / ad7266bcpz-reel7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7266bcpz-reel7.step / ad7266bcpz-reel7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (28 pp, sha256 ef619f55aa5e6d94, retrieved 2026-10-21, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF