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AD7124-8BCPZ-RL7

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Analog Devices Analog To Digital Converters (ADC), LFCSP-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AD7124-8BCPZ-RL7

Analog Devices · Analog To Digital Converters (ADC) · LFCSP-32(5x5)

AD7124-8BCPZ-RL7 from Analog Devices, in a LFCSP-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 REGCAPD power_out Digital LDO regulator output; decouple to DGND with a 0.1 µF capacitor.
2 IOVDD power_in Serial interface supply, 1.65 V to 3.6 V, independent of AVDD.
3 DGND power_in Digital ground reference point.
4 AIN0/IOUT/VBIAS passive Analog input 0 that can also serve as an excitation current output (IOUT0/IOUT1) or a bias voltage output between the two analog supply rails.
5 AIN1/IOUT/VBIAS passive Analog input 1 that can also serve as an excitation current output (IOUT0/IOUT1) or a bias voltage output between the two analog supply rails.
6 AIN2/IOUT/VBIAS/P1 passive Analog input 2 that can also serve as an excitation current output, a bias voltage output, or general-purpose output P1 referenced between AVSS and AVDD.
7 AIN3/IOUT/VBIAS/P2 passive Analog input 3 that can also serve as an excitation current output, a bias voltage output, or general-purpose output P2 referenced between AVSS and AVDD.
8 AIN4/IOUT/VBIAS/P3 passive Analog input 4 that can also serve as an excitation current output, a bias voltage output, or general-purpose output P3 referenced between AVSS and AVDD.
9 AIN5/IOUT/VBIAS/P4 passive Analog input 5 that can also serve as an excitation current output, a bias voltage output, or general-purpose output P4 referenced between AVSS and AVDD.
10 AIN6/IOUT/VBIAS passive Analog input 6 that can also serve as an excitation current output (IOUT0/IOUT1) or a bias voltage output between the two analog supply rails.
11 AIN7/IOUT/VBIAS passive Analog input 7 that can also serve as an excitation current output (IOUT0/IOUT1) or a bias voltage output between the two analog supply rails.
12 REFIN1(+) input Positive reference input for REFIN1; may be between AVDD and AVSS + 1 V, with a nominal 2.5 V reference (REFIN1(+) minus REFIN1(−)) and operation from 1 V to AVDD.
13 REFIN1(−) input Negative reference input; may be any value between AVSS and AVDD − 1 V.
14 AIN8/IOUT/VBIAS passive Analog input 8 that can also serve as an excitation current output (IOUT0/IOUT1) or a bias voltage output between the two analog supply rails.
15 AIN9/IOUT/VBIAS passive Analog input 9 that can also serve as an excitation current output (IOUT0/IOUT1) or a bias voltage output between the two analog supply rails.
16 AIN10/IOUT/VBIAS passive Analog input 10 that can also serve as an excitation current output (IOUT0/IOUT1) or a bias voltage output between the two analog supply rails.
17 AIN11/IOUT/VBIAS passive Analog input 11 that can also serve as an excitation current output (IOUT0/IOUT1) or a bias voltage output between the two analog supply rails.
18 AIN12/IOUT/VBIAS passive Analog input 12 that can also serve as an excitation current output (IOUT0/IOUT1) or a bias voltage output between the two analog supply rails.
19 AIN13/IOUT/VBIAS passive Analog input 13 that can also serve as an excitation current output (IOUT0/IOUT1) or a bias voltage output between the two analog supply rails.
20 AIN14/IOUT/VBIAS/REFIN2(+) passive Analog input 14 that can also serve as an excitation current output, a bias voltage output, or the positive reference input REFIN2(+), which may be between AVDD and AVSS + 1 V with a nominal 2.5 V reference.
21 AIN15/IOUT/VBIAS/REFIN2(−) passive Analog input 15 that can also serve as an excitation current output, a bias voltage output, or the negative reference input REFIN2(−), which may be any value between AVSS and AVDD − 1 V.
22 REFOUT output Buffered output of the internal 2.5 V reference.
23 AVSS power_in Analog supply reference; AVDD − AVSS must be 2.7 V to 3.6 V in low-power or mid-power mode and 2.9 V to 3.6 V in full-power mode, and AVSS may be below 0 V for a dual supply (e.g. −1.8 V).
24 REGCAPA power_out Analog LDO regulator output; decouple to AVSS with a 0.1 µF capacitor.
25 PSW passive Low-side power switch, connected to AVSS, used to switch off a bridge sensor between conversions.
26 AVDD power_in Analog supply voltage, referenced to AVSS.
27 SYNC input Synchronization logic input; when low it resets the digital filter, filter and calibration control logic and holds the modulator in reset, without affecting the digital interface.
28 DOUT/RDY output Serial data output and data-ready output; it goes low when a conversion is complete and returns high before the next update if the result has not been read.
29 DIN input Serial data input to the ADC input shift register, whose contents are transferred to the on-chip control registers.
30 SCLK input Serial clock input with a Schmitt-trigger input, suitable for opto-isolated interfaces; it may be continuous or non-continuous.
31 CLK bidirectional Clock input/output; provides the internal 614.4 kHz clock when enabled, or accepts an external clock when the internal clock is disabled.
32 CS input Active-low chip select input for selecting the ADC; it can be hard-wired low for three-wire operation when SPI diagnostics are not used.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-32(5x5)
Category Data Acquisition
Pins 33

CAD (KiCad official)

  • Symbol: AD7124-8BCPZ-RL7
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: LFCSP-32(5x5) (KiCad packages3D, STEP)
  • 3D model files: ad7124-8bcpz-rl7-etched.step / ad7124-8bcpz-rl7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7124-8bcpz-rl7.step / ad7124-8bcpz-rl7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (91 pp, sha256 750fadb6dc6b4c99, retrieved 2026-10-15, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF