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AD7124-4BRUZ-RL

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Analog Devices Analog To Digital Converters (ADCs), TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AD7124-4BRUZ-RL

Analog Devices · Analog To Digital Converters (ADCs) · TSSOP-24

AD7124-4BRUZ-RL from Analog Devices, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DIN input Serial data input to the ADC input shift register, transferred to the control registers as selected by the communications register bits.
2 SCLK input Serial clock input for data transfers to and from the ADC, with a Schmitt-triggered input suitable for opto-isolated applications.
3 CLK bidirectional Clock input/output; the internal clock can be made available at this pin, or the internal clock can be disabled and the ADC driven by an external clock.
4 CS input Active-low chip select input that selects the ADC; it can be hardwired low when SPI diagnostics are unused for 3-wire operation.
5 REGCAPD power_out Digital LDO regulator output that must be decoupled to DGND with a 0.1 µF capacitor.
6 IOVDD power_in Serial interface supply voltage, 1.65 V to 3.6 V, independent of AVDD.
7 DGND power_in Digital ground reference point.
8 AIN0/IOUT/VBIAS passive Analog input 0, configurable as a positive or negative differential or pseudo-differential terminal, or alternatively as an excitation current (IOUT0/IOUT1) output or bias voltage (VBIAS) output.
9 AIN1/IOUT/VBIAS passive Analog input 1, configurable as a positive or negative differential or pseudo-differential terminal, or alternatively as an excitation current (IOUT0/IOUT1) output or bias voltage (VBIAS) output.
10 AIN2/IOUT/VBIAS/P1 passive Analog input 2, alternatively an excitation current (IOUT0/IOUT1) output or VBIAS output, and can also be configured as general-purpose output P1 referenced between AVSS and AVDD.
11 AIN3/IOUT/VBIAS/P2 passive Analog input 3, alternatively an excitation current (IOUT0/IOUT1) output or VBIAS output, and can also be configured as general-purpose output P2 referenced between AVSS and AVDD.
12 REFIN1(+) passive Positive external reference input, which can be anywhere between AVDD and AVSS + 0.5 V; the nominal reference is 2.5 V and the device functions with a reference from 0.5 V to AVDD.
13 REFIN1(−) passive Negative reference input, which can be anywhere between AVSS and AVDD − 0.5 V.
14 AIN4/IOUT/VBIAS passive Analog input 4, configurable as a positive or negative differential or pseudo-differential terminal, or alternatively as an excitation current (IOUT0/IOUT1) output or bias voltage (VBIAS) output.
15 AIN5/IOUT/VBIAS passive Analog input 5, configurable as a positive or negative differential or pseudo-differential terminal, or alternatively as an excitation current (IOUT0/IOUT1) output or bias voltage (VBIAS) output.
16 AIN6/IOUT/VBIAS/REFIN2(+) passive Analog input 6, alternatively an excitation current or VBIAS output, and also the positive reference input for REFIN2(±), which can be anywhere between AVDD and AVSS + 0.5 V.
17 AIN7/IOUT/VBIAS/REFIN2(−) passive Analog input 7, alternatively an excitation current or VBIAS output, and also the negative reference input for REFIN2(±), which can be anywhere between AVSS and AVDD − 0.5 V.
18 REFOUT power_out Buffered output of the internal 2.5 V voltage reference.
19 AVSS power_in Analog supply voltage reference; AVDD − AVSS must be 2.7 V to 3.6 V in mid or low power mode and 2.9 V to 3.6 V in full power mode, and AVSS can be taken below 0 V for a ±1.8 V dual supply.
20 REGCAPA power_out Analog LDO regulator output that must be decoupled to AVSS with a 0.1 µF capacitor.
21 PSW passive Low-side power switch to AVSS, which can carry up to 30 mA continuous current.
22 AVDD power_in Analog supply voltage, relative to AVSS.
23 SYNC input Logic input for synchronizing the digital filters and analog modulators across multiple devices; when low it resets the filter, filter control and calibration control logic and holds the modulator in reset, and it resets RDY high.
24 DOUT/RDY output Serial data output that also serves as the data-ready output, going low to indicate conversion completion and returning high if the data is not read before the next update.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package TSSOP-24
Category ADC/DAC/Data Conversion
Pins 24

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
AVDD to AVSS -0.3 3.96 V TA = 25°C, unless otherwise noted 14
IOVDD to DGND -0.3 3.96 V TA = 25°C, unless otherwise noted 14
IOVDD to AVSS -0.3 5.94 V TA = 25°C, unless otherwise noted 14
AVSS to DGND -1.98 0.3 V TA = 25°C, unless otherwise noted 14
Digital Input Voltage to DGND (max IOVDD + 0.3 V, not numeric) -0.3 V TA = 25°C, unless otherwise noted 14
Digital Output Voltage to DGND (max IOVDD + 0.3 V, not numeric) -0.3 V TA = 25°C, unless otherwise noted 14
AINx/Digital Input Current 10 mA TA = 25°C, unless otherwise noted 14
Operating Temperature Range -40 125 °C TA = 25°C, unless otherwise noted 14
Storage Temperature Range -65 150 °C TA = 25°C, unless otherwise noted 14
Maximum Junction Temperature 150 °C TA = 25°C, unless otherwise noted 14
ESD Human Body Model (HBM) 4 kV TA = 25°C, unless otherwise noted 14
Absolute Input Current, Low Power Mode -1 1 nA Gain > 1 or Gain = 1 (Buffered), Low Power Mode 7
Differential Input Current, Low Power Mode -0.2 0.2 nA Gain > 1 or Gain = 1 (Buffered), Low Power Mode 7
Absolute Input Current, Mid Power Mode -1.2 1.2 nA Gain > 1 or Gain = 1 (Buffered), Mid Power Mode 7
Differential Input Current, Mid Power Mode -0.4 0.4 nA Gain > 1 or Gain = 1 (Buffered), Mid Power Mode 7
Absolute Input Current, Full Power Mode -3.3 3.3 nA Gain > 1 or Gain = 1 (Buffered), Full Power Mode 7
Differential Input Current, Full Power Mode -1.5 1.5 nA Gain > 1 or Gain = 1 (Buffered), Full Power Mode 7
Absolute Input Current, Gain = 1 (Unbuffered) -2.65 2.65 µA/V Gain = 1 (Unbuffered); current varies with input voltage 7
Internal Reference Initial Accuracy (2.5 V nominal) -0.2 0.2 % TA = 25°C 7
Internal Reference Drift (TSSOP) 10 ppm/°C TSSOP 7
External REFIN Voltage 0.5 2.5 V REFIN = REFINx(+) − REFINx(−); maximum printed as AVDD (not numeric) 7
Reference Input Absolute Input Current, Buffered, Low Power Mode -0.5 0.5 nA Buffered; Low Power Mode 7
Reference Input Absolute Input Current, Buffered, Mid Power Mode -1 1 nA Buffered; Mid Power Mode 7
Reference Input Absolute Input Current, Buffered, Full Power Mode -3 3 nA Buffered; Full Power Mode 7
Excitation Current Initial Tolerance -4 4 % TA = 25°C 8
Excitation Current Matching (IOUT0 vs IOUT1) -0.5 0.5 % Matching between IOUT0 and IOUT1, VOUT = 0 V 8
Excitation Current Drift Matching 5 30 ppm/°C 8
Temperature Sensor Accuracy -0.5 0.5 °C 8
Low-Side Power Switch On Resistance (RON) RON 7 10 Ω 8
Internal Clock Frequency Tolerance (nominal 614.4 kHz) -5 5 % Nominal 614.4 kHz 8
Reference Detect Level 0.7 1 V REF_DET_ERR bit active if VREF < 0.7 V 8
Logic Input Low Voltage, VINL VINL 0.7 V 2.3 V ≤ IOVDD ≤ 3.6 V 9
Logic Input High Voltage, VINH VINH 2 V 2.7 V ≤ IOVDD ≤ 3.6 V 9
Logic Input High Voltage, VINH VINH 1.7 V 2.3 V ≤ IOVDD < 2.7 V 9
Logic Input Hysteresis 0.2 0.6 V 1.65 V ≤ IOVDD ≤ 3.6 V 9
Logic Input Currents -1 1 µA VIN = IOVDD or GND 9
Logic Output Low Voltage, VOL VOL 0.4 V ISINK = 100 µA 9
Floating State Leakage Current -1 1 µA 9
AVDD to AVSS Supply, Low Power Mode 2.7 3.6 V Low Power Mode 9
AVDD to AVSS Supply, Mid Power Mode 2.7 3.6 V Mid Power Mode 9
AVDD to AVSS Supply, Full Power Mode 2.9 3.6 V Full Power Mode 9
IOVDD to GND Supply IOVDD 1.65 3.6 V 9
AVSS to GND AVSS -1.8 0 V 9
IAVDD External Reference, Gain = 16 to 128 IAVDD 235 300 µA External reference; Low Power Mode 9
IAVDD External Reference, Gain = 16 to 128 IAVDD 330 430 µA External reference; Mid Power Mode 9
IAVDD External Reference, Gain = 16 to 128 IAVDD 875 1200 µA External reference; Full Power Mode 10
IAVDD Increase Due to Internal Reference IAVDD 50 70 µA Independent of power mode 10
IIOVDD, Low Power Mode IIOVDD 20 35 µA Low Power Mode 10
IIOVDD, Mid Power Mode IIOVDD 25 40 µA Mid Power Mode 10
IIOVDD, Full Power Mode IIOVDD 55 80 µA Full Power Mode 10
Standby Current IAVDD IAVDD 7 15 µA LDOs on only 10
Standby Current IIOVDD IIOVDD 8 20 µA 10
Power-Down Current IAVDD IAVDD 1 3 µA Independent of power mode 10
Power-Down Current IIOVDD IIOVDD 1 2 µA Independent of power mode 10
Thermal Resistance Junction-to-Ambient (θJA) θJA 73.5 °C/W 24-Lead TSSOP; JEDEC 2S2P board, natural convection 14
Thermal Resistance Junction-to-Board (θJB) θJB 27.5 °C/W 24-Lead TSSOP; JEDEC 2S2P board, natural convection 14
Thermal Resistance Junction-to-Case Top (θJC_top) θJC_top 15 °C/W 24-Lead TSSOP; JEDEC 2S2P board, natural convection 14

CAD (KiCad official)

  • Symbol: AD7124-4BRUZ-RL
  • Footprint: Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm
  • 3D model: TSSOP-24 (KiCad packages3D, STEP)
  • 3D model files: ad7124-4bruz-rl-etched.step / ad7124-4bruz-rl-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7124-4bruz-rl.step / ad7124-4bruz-rl.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (94 pp, sha256 8a9194657efa8d5c, retrieved 2026-10-29, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF