component
AD7124-4BCPZ-RL7
Public Made by Adomby adom
Analog Devices Analog To Digital Converters (ADC), LFCSP-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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"title": "AD7124-4BCPZ-RL7",
"brief": "Analog Devices Analog To Digital Converters (ADC), LFCSP-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"version": "0.1.0",
"license": "CC-BY-SA-4.0",
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"data acquisition",
"ad7124-4bcpz-rl7",
"factory-2.0.0",
"extractor-text"
],
"component": {
"mpn": "AD7124-4BCPZ-RL7",
"manufacturer": "Analog Devices",
"package": "LFCSP-32(5x5)",
"pin_count": 33,
"category": "Data Acquisition",
"subcategory": "Analog To Digital Converters (ADC)",
"datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588885971949928448",
"parts": {
"symbol": "ad7124-4bcpz-rl7.kicad_sym",
"footprint": "ad7124-4bcpz-rl7.kicad_mod",
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"lbr": "ad7124-4bcpz-rl7.lbr"
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"distributor_links": {
"lcsc": "C514233",
"digikey": "505-AD7124-4BCPZ-RL7TR-ND"
},
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"checked_at": "2026-10-18T19:18:55Z",
"source": "Component Ocean /api/assign-pns",
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"pn": "505-AD7124-4BCPZ-RL7TR-ND",
"status": "found"
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"pn": null,
"status": "quota"
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},
"pins": [
{
"number": "1",
"name": "REGCAPD",
"type": "power_out",
"description": "Digital LDO regulator output; decouple this pin to DGND with a 0.1 µF capacitor."
},
{
"number": "2",
"name": "IOVDD",
"type": "power_in",
"description": "Serial interface supply voltage, 1.65 V to 3.6 V, independent of AVDD."
},
{
"number": "3",
"name": "DGND",
"type": "power_in",
"description": "Digital ground reference point."
},
{
"number": "4",
"name": "AIN0/IOUT/VBIAS",
"type": "passive",
"description": "Analog Input 0, also selectable as an excitation current output (IOUT0/IOUT1) or bias voltage (VBIAS) output midway between the analog supply rails; configured as the positive or negative input of a differential or pseudo differential input."
},
{
"number": "5",
"name": "AIN1/IOUT/VBIAS",
"type": "passive",
"description": "Analog Input 1, also selectable as an excitation current output (IOUT0/IOUT1) or bias voltage (VBIAS) output midway between the analog supply rails; configured as the positive or negative input of a differential or pseudo differential input."
},
{
"number": "6",
"name": "DNC",
"type": "unconnected",
"description": "Do not connect to this pin."
},
{
"number": "7",
"name": "DNC",
"type": "unconnected",
"description": "Do not connect to this pin."
},
{
"number": "8",
"name": "AIN2/IOUT/VBIAS/P1",
"type": "passive",
"description": "Analog Input 2, also selectable as an excitation current output, bias voltage output, or general-purpose output P1 referenced between AVSS and AVDD; configured as the positive or negative input of a differential or pseudo differential input."
},
{
"number": "9",
"name": "AIN3/IOUT/VBIAS/P2",
"type": "passive",
"description": "Analog Input 3, also selectable as an excitation current output, bias voltage output, or general-purpose output P2 referenced between AVSS and AVDD; configured as the positive or negative input of a differential or pseudo differential input."
},
{
"number": "10",
"name": "DNC",
"type": "unconnected",
"description": "Do not connect to this pin."
},
{
"number": "11",
"name": "DNC",
"type": "unconnected",
"description": "Do not connect to this pin."
},
{
"number": "12",
"name": "REFIN1(+)",
"type": "passive",
"description": "Positive reference input; the reference (REFIN1(+) − REFIN1(−)) is nominally 2.5 V and the device functions with a reference from 0.5 V to AVDD, with REFIN1(+) anywhere between AVDD and AVSS + 0.5 V."
},
{
"number": "13",
"name": "REFIN1(−)",
"type": "passive",
"description": "Negative reference input, which can be anywhere between AVSS and AVDD − 0.5 V."
},
{
"number": "14",
"name": "DNC",
"type": "unconnected",
"description": "Do not connect to this pin."
},
{
"number": "15",
"name": "DNC",
"type": "unconnected",
"description": "Do not connect to this pin."
},
{
"number": "16",
"name": "AIN4/IOUT/VBIAS",
"type": "passive",
"description": "Analog Input 4, also selectable as an excitation current output or bias voltage output midway between the analog supply rails; configured as the positive or negative input of a differential or pseudo differential input."
},
{
"number": "17",
"name": "AIN5/IOUT/VBIAS",
"type": "passive",
"description": "Analog Input 5, also selectable as an excitation current output or bias voltage output midway between the analog supply rails; configured as the positive or negative input of a differential or pseudo differential input."
},
{
"number": "18",
"name": "DNC",
"type": "unconnected",
"description": "Do not connect to this pin."
},
{
"number": "19",
"name": "DNC",
"type": "unconnected",
"description": "Do not connect to this pin."
},
{
"number": "20",
"name": "AIN6/IOUT/VBIAS/REFIN2(+)",
"type": "passive",
"description": "Analog Input 6, also selectable as an excitation current output, bias voltage output, or positive reference input REFIN2(+), which can be anywhere between AVDD and AVSS + 0.5 V with a nominal 2.5 V reference."
},
{
"number": "21",
"name": "AIN7/IOUT/VBIAS/REFIN2(−)",
"type": "passive",
"description": "Analog Input 7, also selectable as an excitation current output, bias voltage output, or negative reference input REFIN2(−), which can be anywhere between AVSS and AVDD − 0.5 V."
},
{
"number": "22",
"name": "REFOUT",
"type": "power_out",
"description": "Buffered output of the internal 2.5 V voltage reference."
},
{
"number": "23",
"name": "AVSS",
"type": "power_in",
"description": "Analog supply voltage reference; AVDD − AVSS must be 2.7 V to 3.6 V in mid or low power mode and 2.9 V to 3.6 V in full power mode, and AVSS can be taken below 0 V for a dual supply (for example −1.8 V)."
},
{
"number": "24",
"name": "REGCAPA",
"type": "power_out",
"description": "Analog LDO regulator output; decouple this pin to AVSS with a 0.1 µF capacitor."
},
{
"number": "25",
"name": "PSW",
"type": "passive",
"description": "Low-side power switch to AVSS, with on resistance of 10 Ω maximum and allowable continuous current of 30 mA."
},
{
"number": "26",
"name": "AVDD",
"type": "power_in",
"description": "Analog supply voltage, relative to AVSS."
},
{
"number": "27",
"name": "SYNC",
"type": "input",
"description": "Synchronization logic input; when low it resets the digital filter, filter and calibration control logic and holds the modulator in reset, and it resets RDY high if low."
},
{
"number": "28",
"name": "DOUT/RDY",
"type": "output",
"description": "Serial data output and data ready output; goes low to indicate conversion completion and is valid on the SCLK rising edge when CS is low."
},
{
"number": "29",
"name": "DIN",
"type": "input",
"description": "Serial data input to the ADC input shift register."
},
{
"number": "30",
"name": "SCLK",
"type": "input",
"description": "Serial clock input for data transfers to and from the ADC, with a Schmitt-triggered input."
},
{
"number": "31",
"name": "CLK",
"type": "bidirectional",
"description": "Clock input/clock output; the internal 614.4 kHz clock can be made available here, or the ADC can be driven by an external clock."
},
{
"number": "32",
"name": "CS",
"type": "input",
"description": "Active-low chip select input that selects the ADC; can be hardwired low when SPI diagnostics are unused."
},
{
"number": "33",
"name": "EP",
"type": "passive",
"description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The AD7124-4BCPZ-RL7 is ordered in the CP-32-12 (0.75 mm height) LFCSP outline. Table 7 and Figure 9; Pins 6, 7, 10, 11, 14, 15, 18 and 19 are listed in the datasheet as DNC (do not connect) and are ent; The exposed pad is not numbered in the datasheet; it is listed as 'EP' and is recorded as AVSS per t",
"exposed pad 33 added from the footprint",
"dropped thermal pad ['EP'] absent from footprint"
],
"pages_sent": 20,
"cost_usd": 0.1486,
"at": "2026-10-18T19:16:40"
},
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"described": 33,
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"refuses_to_fabricate": true
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"metadata": {
"specs": {
"Manufacturer": "Analog Devices",
"Package": "LFCSP-32(5x5)",
"Category": "Data Acquisition",
"Pins": "33"
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"name": "Absolute analog input current (low power mode)",
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{
"name": "External REFIN voltage",
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"max": null,
"conditions": "REFIN = REFINx(+) − REFINx(−); printed max is AVDD",
"source_page": 8,
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{
"name": "Reference input current (buffered, low power mode)",
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"typ": null,
"max": 0.5,
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{
"name": "Reference input current (buffered, mid power mode)",
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"typ": null,
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"conditions": "Buffered, Mid Power Mode",
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"name": "Reference input current (buffered, full power mode)",
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"min": -3,
"typ": null,
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"conditions": "Buffered, Full Power Mode",
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"name": "Excitation current initial tolerance",
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"name": "Excitation current matching",
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{
"name": "Low-side power switch on resistance",
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{
"name": "Reference detect level",
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{
"name": "Logic input low voltage",
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{
"name": "Logic input high voltage",
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{
"name": "Logic output low voltage (including CLK)",
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{
"name": "AVDD to AVSS supply voltage",
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