component
AD7124-4BCPZ-RL7
Public Made by Adomby adom
Analog Devices Analog To Digital Converters (ADC), LFCSP-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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PCB Footprint
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Datasheet
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README
markdownAD7124-4BCPZ-RL7
Analog Devices · Analog To Digital Converters (ADC) · LFCSP-32(5x5)
AD7124-4BCPZ-RL7 from Analog Devices, in a LFCSP-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | REGCAPD | power_out | Digital LDO regulator output; decouple this pin to DGND with a 0.1 µF capacitor. |
| 2 | IOVDD | power_in | Serial interface supply voltage, 1.65 V to 3.6 V, independent of AVDD. |
| 3 | DGND | power_in | Digital ground reference point. |
| 4 | AIN0/IOUT/VBIAS | passive | Analog Input 0, also selectable as an excitation current output (IOUT0/IOUT1) or bias voltage (VBIAS) output midway between the analog supply rails; configured as the positive or negative input of a differential or pseudo differential input. |
| 5 | AIN1/IOUT/VBIAS | passive | Analog Input 1, also selectable as an excitation current output (IOUT0/IOUT1) or bias voltage (VBIAS) output midway between the analog supply rails; configured as the positive or negative input of a differential or pseudo differential input. |
| 6 | DNC | unconnected | Do not connect to this pin. |
| 7 | DNC | unconnected | Do not connect to this pin. |
| 8 | AIN2/IOUT/VBIAS/P1 | passive | Analog Input 2, also selectable as an excitation current output, bias voltage output, or general-purpose output P1 referenced between AVSS and AVDD; configured as the positive or negative input of a differential or pseudo differential input. |
| 9 | AIN3/IOUT/VBIAS/P2 | passive | Analog Input 3, also selectable as an excitation current output, bias voltage output, or general-purpose output P2 referenced between AVSS and AVDD; configured as the positive or negative input of a differential or pseudo differential input. |
| 10 | DNC | unconnected | Do not connect to this pin. |
| 11 | DNC | unconnected | Do not connect to this pin. |
| 12 | REFIN1(+) | passive | Positive reference input; the reference (REFIN1(+) − REFIN1(−)) is nominally 2.5 V and the device functions with a reference from 0.5 V to AVDD, with REFIN1(+) anywhere between AVDD and AVSS + 0.5 V. |
| 13 | REFIN1(−) | passive | Negative reference input, which can be anywhere between AVSS and AVDD − 0.5 V. |
| 14 | DNC | unconnected | Do not connect to this pin. |
| 15 | DNC | unconnected | Do not connect to this pin. |
| 16 | AIN4/IOUT/VBIAS | passive | Analog Input 4, also selectable as an excitation current output or bias voltage output midway between the analog supply rails; configured as the positive or negative input of a differential or pseudo differential input. |
| 17 | AIN5/IOUT/VBIAS | passive | Analog Input 5, also selectable as an excitation current output or bias voltage output midway between the analog supply rails; configured as the positive or negative input of a differential or pseudo differential input. |
| 18 | DNC | unconnected | Do not connect to this pin. |
| 19 | DNC | unconnected | Do not connect to this pin. |
| 20 | AIN6/IOUT/VBIAS/REFIN2(+) | passive | Analog Input 6, also selectable as an excitation current output, bias voltage output, or positive reference input REFIN2(+), which can be anywhere between AVDD and AVSS + 0.5 V with a nominal 2.5 V reference. |
| 21 | AIN7/IOUT/VBIAS/REFIN2(−) | passive | Analog Input 7, also selectable as an excitation current output, bias voltage output, or negative reference input REFIN2(−), which can be anywhere between AVSS and AVDD − 0.5 V. |
| 22 | REFOUT | power_out | Buffered output of the internal 2.5 V voltage reference. |
| 23 | AVSS | power_in | Analog supply voltage reference; AVDD − AVSS must be 2.7 V to 3.6 V in mid or low power mode and 2.9 V to 3.6 V in full power mode, and AVSS can be taken below 0 V for a dual supply (for example −1.8 V). |
| 24 | REGCAPA | power_out | Analog LDO regulator output; decouple this pin to AVSS with a 0.1 µF capacitor. |
| 25 | PSW | passive | Low-side power switch to AVSS, with on resistance of 10 Ω maximum and allowable continuous current of 30 mA. |
| 26 | AVDD | power_in | Analog supply voltage, relative to AVSS. |
| 27 | SYNC | input | Synchronization logic input; when low it resets the digital filter, filter and calibration control logic and holds the modulator in reset, and it resets RDY high if low. |
| 28 | DOUT/RDY | output | Serial data output and data ready output; goes low to indicate conversion completion and is valid on the SCLK rising edge when CS is low. |
| 29 | DIN | input | Serial data input to the ADC input shift register. |
| 30 | SCLK | input | Serial clock input for data transfers to and from the ADC, with a Schmitt-triggered input. |
| 31 | CLK | bidirectional | Clock input/clock output; the internal 614.4 kHz clock can be made available here, or the ADC can be driven by an external clock. |
| 32 | CS | input | Active-low chip select input that selects the ADC; can be hardwired low when SPI diagnostics are unused. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LFCSP-32(5x5) |
| Category | Data Acquisition |
| Pins | 33 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Absolute analog input current (low power mode) | -1 | 1 | nA | Gain > 1 or Gain = 1 (Buffered), Low Power Mode | 8 | ||
| Differential analog input current (low power mode) | -0.2 | 0.2 | nA | Gain > 1 or Gain = 1 (Buffered), Low Power Mode | 8 | ||
| Absolute analog input current (mid power mode) | -1.2 | 1.2 | nA | Gain > 1 or Gain = 1 (Buffered), Mid Power Mode | 8 | ||
| Differential analog input current (mid power mode) | -0.4 | 0.4 | nA | Gain > 1 or Gain = 1 (Buffered), Mid Power Mode | 8 | ||
| Absolute analog input current (full power mode) | -3.3 | 3.3 | nA | Gain > 1 or Gain = 1 (Buffered), Full Power Mode | 8 | ||
| Differential analog input current (full power mode) | -1.5 | 1.5 | nA | Gain > 1 or Gain = 1 (Buffered), Full Power Mode | 8 | ||
| Absolute analog input current (unbuffered) | -2.65 | 2.65 | µA/V | Gain = 1 (Unbuffered); current varies with input voltage | 8 | ||
| Internal reference initial accuracy | -0.2 | 0.2 | % | TA = 25°C | 8 | ||
| Internal reference drift | 2 | 15 | ppm/°C | AD7124-4, LFCSP package | 8 | ||
| External REFIN voltage | 0.5 | 2.5 | V | REFIN = REFINx(+) − REFINx(−); printed max is AVDD | 8 | ||
| Reference input current (buffered, low power mode) | -0.5 | 0.5 | nA | Buffered, Low Power Mode | 8 | ||
| Reference input current (buffered, mid power mode) | -1 | 1 | nA | Buffered, Mid Power Mode | 8 | ||
| Reference input current (buffered, full power mode) | -3 | 3 | nA | Buffered, Full Power Mode | 8 | ||
| Excitation current initial tolerance | -4 | 4 | % | TA = 25°C | 9 | ||
| Excitation current matching | -0.5 | 0.5 | % | Matching between IOUT0 and IOUT1, VOUT = 0 V | 9 | ||
| Excitation current drift matching | 5 | 30 | ppm/°C | 9 | |||
| Temperature sensor accuracy | -0.5 | 0.5 | °C | 9 | |||
| Low-side power switch on resistance | RON | 7 | 10 | Ω | 9 | ||
| Reference detect level | 0.7 | 1 | V | REF_DET_ERR bit active if VREF < 0.7 V | 9 | ||
| Internal clock frequency tolerance | -5 | 5 | % | Internal clock, 614.4 kHz nominal | 9 | ||
| Logic input low voltage | VINL | 0.7 | V | 2.3 V ≤ IOVDD ≤ 3.6 V | 9 | ||
| Logic input high voltage | VINH | 1.7 | V | 2.3 V ≤ IOVDD < 2.7 V | 9 | ||
| Logic input high voltage | VINH | 2 | V | 2.7 V ≤ IOVDD ≤ 3.6 V | 9 | ||
| Logic input hysteresis | 0.2 | 0.6 | V | 1.65 V ≤ IOVDD ≤ 3.6 V | 9 | ||
| Digital input currents | -1 | 1 | µA | VIN = IOVDD or GND | 9 | ||
| Digital output low voltage (P1, P2) | VOL | 0.4 | V | ISINK = 100 µA | 9 | ||
| Logic output low voltage (including CLK) | VOL | 0.4 | V | ISINK = 100 µA | 10 | ||
| AVDD to AVSS supply voltage | 2.7 | 3.6 | V | Low Power Mode | 10 | ||
| AVDD to AVSS supply voltage | 2.9 | 3.6 | V | Full Power Mode | 10 | ||
| IOVDD to GND supply voltage | IOVDD | 1.65 | 3.6 | V | 10 | ||
| AVSS to GND voltage | AVSS | -1.8 | 0 | V | 10 | ||
| IAVDD (external reference, gain = 12) | IAVDD | 125 | 140 | µA | Low Power Mode; Gain = 12; all buffers off | 10 | |
| IAVDD increase per AINx buffer | IAVDD | 15 | 25 | µA | Low Power Mode; Gain = 1 | 10 | |
| IAVDD (external reference, gain = 2 to 8) | IAVDD | 205 | 250 | µA | Low Power Mode; Gain = 2 to 8 | 10 | |
| IAVDD (external reference, gain = 16 to 128) | IAVDD | 235 | 300 | µA | Low Power Mode; Gain = 16 to 128 | 10 | |
| IAVDD (external reference, gain = 12) | IAVDD | 150 | 170 | µA | Mid Power Mode; Gain = 12; all buffers off | 10 | |
| IAVDD increase per AINx buffer | IAVDD | 30 | 40 | µA | Mid Power Mode; Gain = 1 | 10 | |
| IAVDD (external reference, gain = 2 to 8) | IAVDD | 275 | 345 | µA | Mid Power Mode; Gain = 2 to 8 | 10 | |
| IAVDD (external reference, gain = 16 to 128) | IAVDD | 330 | 430 | µA | Mid Power Mode; Gain = 16 to 128 | 10 | |
| IAVDD (external reference, gain = 12) | IAVDD | 315 | 350 | µA | Full Power Mode; Gain = 12; all buffers off | 10 | |
| IAVDD increase per AINx buffer | IAVDD | 90 | 135 | µA | Full Power Mode; Gain = 1 | 10 | |
| IAVDD (external reference, gain = 2 to 8) | IAVDD | 660 | 830 | µA | Full Power Mode; Gain = 2 to 8 | 10 | |
| IAVDD (external reference, gain = 16 to 128) | IAVDD | 875 | 1200 | µA | Full Power Mode; Gain = 16 to 128 | 10 | |
| IAVDD increase due to internal reference | IAVDD | 50 | 70 | µA | Independent of power mode; reference buffers not required with this reference | 10 | |
| IIOVDD supply current | IIOVDD | 20 | 35 | µA | Low Power Mode | 10 | |
| IIOVDD supply current | IIOVDD | 25 | 40 | µA | Mid Power Mode | 10 | |
| IIOVDD supply current | IIOVDD | 55 | 80 | µA | Full Power Mode | 10 | |
| Standby current (IAVDD) | IAVDD | 7 | 15 | µA | LDOs on only | 11 | |
| Power-down current (IAVDD) | IAVDD | 1 | 3 | µA | Independent of power mode | 11 | |
| AVDD to AVSS absolute maximum rating | -0.3 | 3.96 | V | TA = 25°C, unless otherwise noted | 14 | ||
| IOVDD to DGND absolute maximum rating | -0.3 | 3.96 | V | TA = 25°C, unless otherwise noted | 14 | ||
| IOVDD to AVSS absolute maximum rating | -0.3 | 5.94 | V | TA = 25°C, unless otherwise noted | 14 | ||
| AVSS to DGND absolute maximum rating | -1.98 | 0.3 | V | TA = 25°C, unless otherwise noted | 14 | ||
| AINx/digital input current | 10 | mA | 14 | ||||
| Operating temperature range | -40 | 125 | °C | 14 | |||
| Storage temperature range | -65 | 150 | °C | 14 | |||
| Maximum junction temperature | 150 | °C | 14 | ||||
| Junction-to-ambient thermal resistance (32-lead LFCSP) | θJA | 32.5 | °C/W | Device soldered in circuit board (surface-mount) | 14 | ||
| Junction-to-case thermal resistance (32-lead LFCSP) | θJC | 32.71 | °C/W | 14 |
CAD (KiCad official)
- Symbol:
AD7124-4BCPZ-RL7 - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: LFCSP-32(5x5) (KiCad packages3D, STEP)
- 3D model files:
ad7124-4bcpz-rl7-etched.step/ad7124-4bcpz-rl7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad7124-4bcpz-rl7.step/ad7124-4bcpz-rl7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (93 pp, sha256
9f9df9294d9f4ad3, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).