component
AD5761BRUZ
Public Made by Adomby adom
Analog Devices Digital To Analog Converters (DACs), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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"component": {
"mpn": "AD5761BRUZ",
"manufacturer": "Analog Devices",
"package": "TSSOP-16",
"pin_count": 16,
"category": "Data Converters",
"subcategory": "Digital To Analog Converters (DACs)",
"datasheet": "https://www.analog.com/media/en/technical-documentation/data-sheets/AD5761_5721.pdf",
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"distributor_links": {
"lcsc": "C650244",
"digikey": "505-AD5761BRUZ-ND",
"mouser": "584-AD5761BRUZ"
},
"distributor_check": {
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"pins": [
{
"number": "1",
"name": "ALERT",
"type": "output",
"description": "Active-low alert output asserted when die temperature exceeds approximately 150°C, on output short circuit or brownout, and during power-up or a full software/hardware reset until a control register write sets it high."
},
{
"number": "2",
"name": "CLEAR",
"type": "input",
"description": "Falling-edge clear input that sets the DAC register to zero-scale, midscale, or full-scale code (user selectable) and updates the DAC output; can be left floating due to an internal pull-up resistor."
},
{
"number": "3",
"name": "RESET",
"type": "input",
"description": "Active-low reset input that returns the device to its default power-on state with the output clamped to ground and the output buffer powered down; can be left floating due to an internal pull-up resistor."
},
{
"number": "4",
"name": "VREFIN",
"type": "input",
"description": "External reference voltage input; VREFIN = 2.5 V for specified performance."
},
{
"number": "5",
"name": "AGND",
"type": "power_in",
"description": "Ground reference for analog circuitry."
},
{
"number": "6",
"name": "VSS",
"type": "power_in",
"description": "Negative analog supply accepting −16.5 V to 0 V (connect to 0 V for unipolar output ranges) and must be decoupled to AGND."
},
{
"number": "7",
"name": "VOUT",
"type": "output",
"description": "Analog output voltage of the DAC; the output amplifier can directly drive a 2 kΩ, 1 nF load."
},
{
"number": "8",
"name": "VDD",
"type": "power_in",
"description": "Positive analog supply of 4.75 V to 30 V for unipolar ranges or 4.75 V to 16.5 V for bipolar ranges, and must be decoupled to AGND."
},
{
"number": "9",
"name": "DNC",
"type": "unconnected",
"description": "Do not connect to this pin."
},
{
"number": "10",
"name": "SDO",
"type": "output",
"description": "Serial data output that clocks data from the serial register in daisy-chain or readback mode, changing on the rising edge of SCLK and valid on the falling edge."
},
{
"number": "11",
"name": "LDAC",
"type": "input",
"description": "Load DAC logic input that updates the DAC register and analog output; tied low it updates with the input register, held high it holds off the update until the falling edge, and it can be left floating due to an internal pull-up resistor."
},
{
"number": "12",
"name": "SDI",
"type": "input",
"description": "Serial data input; data must be valid on the falling edge of SCLK."
},
{
"number": "13",
"name": "SYNC",
"type": "input",
"description": "Active-low frame synchronization input; data is transferred in on SCLK falling edges while SYNC is low and latched on the rising edge of SYNC."
},
{
"number": "14",
"name": "SCLK",
"type": "input",
"description": "Serial clock input with data clocked into the input shift register on the falling edge, operating at up to 50 MHz."
},
{
"number": "15",
"name": "DVCC",
"type": "power_in",
"description": "Digital supply of 1.7 V to 5.5 V that sets the voltage at which the digital interface operates."
},
{
"number": "16",
"name": "DGND",
"type": "power_in",
"description": "Digital ground."
}
],
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"guards": "pin_guards 0.1: passed",
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"pages_sent": 8,
"cost_usd": 0.1086,
"at": "2026-10-31T12:40:18"
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"datasheet": {
"url": "https://www.analog.com/media/en/technical-documentation/data-sheets/AD5761_5721.pdf",
"pages": 31,
"sha256": "5df86567a5eabe16",
"source_tier": "mfr"
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"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 16,
"described": 16,
"cites_pages": true,
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"seat": "z = 0",
"extents_mm": [
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1.1
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"zmin_mm": -0.0,
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