AD5761BRUZ from Analog Devices, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	ALERT	output	Active-low alert output asserted when die temperature exceeds approximately 150°C, on output short circuit or brownout, and during power-up or a full software/hardware reset until a control register write sets it high.
2	CLEAR	input	Falling-edge clear input that sets the DAC register to zero-scale, midscale, or full-scale code (user selectable) and updates the DAC output; can be left floating due to an internal pull-up resistor.
3	RESET	input	Active-low reset input that returns the device to its default power-on state with the output clamped to ground and the output buffer powered down; can be left floating due to an internal pull-up resistor.
4	VREFIN	input	External reference voltage input; VREFIN = 2.5 V for specified performance.
5	AGND	power_in	Ground reference for analog circuitry.
6	VSS	power_in	Negative analog supply accepting −16.5 V to 0 V (connect to 0 V for unipolar output ranges) and must be decoupled to AGND.
7	VOUT	output	Analog output voltage of the DAC; the output amplifier can directly drive a 2 kΩ, 1 nF load.
8	VDD	power_in	Positive analog supply of 4.75 V to 30 V for unipolar ranges or 4.75 V to 16.5 V for bipolar ranges, and must be decoupled to AGND.
9	DNC	unconnected	Do not connect to this pin.
10	SDO	output	Serial data output that clocks data from the serial register in daisy-chain or readback mode, changing on the rising edge of SCLK and valid on the falling edge.
11	LDAC	input	Load DAC logic input that updates the DAC register and analog output; tied low it updates with the input register, held high it holds off the update until the falling edge, and it can be left floating due to an internal pull-up resistor.
12	SDI	input	Serial data input; data must be valid on the falling edge of SCLK.
13	SYNC	input	Active-low frame synchronization input; data is transferred in on SCLK falling edges while SYNC is low and latched on the rising edge of SYNC.
14	SCLK	input	Serial clock input with data clocked into the input shift register on the falling edge, operating at up to 50 MHz.
15	DVCC	power_in	Digital supply of 1.7 V to 5.5 V that sets the voltage at which the digital interface operates.
16	DGND	power_in	Digital ground.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	TSSOP-16
Category	Data Converters
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Relative Accuracy INL, B Grade	INL	-2		2	LSB	All ranges except 0 V to 16 V and 0 V to 20 V, VREFIN = 2.5 V external reference	3
Differential Nonlinearity	DNL	-1		1	LSB		3
Zero-Scale Error		-6		6	mV	All ranges except ±10 V and 0 V to 20 V, external reference	3
Zero-Scale Error (0 V to 20 V, ±10 V)		-10		10	mV	0 V to 20 V, ±10 V ranges, external reference	3
Bipolar Zero Error		-5		5	mV	All bipolar ranges except ±10 V	3
Bipolar Zero Error (±10 V)		-7		7	mV	±10 V output range	3
Offset Error		-6		6	mV	All ranges except ±10 V and 0 V to 20 V, external reference	3
Offset Error (0 V to 20 V, ±10 V)		-10		10	mV	0 V to 20 V, ±10 V ranges; external reference	3
Gain Error		-0.1		0.1	% FSR	External reference	3
Total Unadjusted Error	TUE	-0.1		0.1	% FSR	External reference	3
Reference Input Current		-2	0.5	2	µA		3
Reference Range		2		3	V		3
Output Voltage Range		-10		10	V	VDD/VSS = ±11 V, ±10 V output range	3
Output Voltage Range with 5% overrange		-10.5		10.5	V	VDD/VSS = ±11 V, ±10 V output range with 5% overrange	3
Logic Input Voltage High	VIH	0.7			×DVCC	DVCC = 1.7 V to 5.5 V, JEDEC compliant	4
Logic Input Voltage Low	VIL			0.3	×DVCC	DVCC = 1.7 V to 5.5 V, JEDEC compliant	4
Input Leakage Current (SDI, SCLK, SYNC)		-1		1	µA	SDI, SCLK, SYNC	4
Input Leakage Current (LDAC, CLEAR, RESET high)		-1		1	µA	LDAC, CLEAR, RESET pins held high	4
Logic Output Voltage Low	VOL			0.4	V	DVCC = 1.7 V to 5.5 V, sinking 200 µA	4
SDO High Impedance Leakage Current		-1		1	µA		4
VDD	VDD	4.75		30	V		4
VSS	VSS	-16.5		0	V		4
DVCC	DVCC	1.7		5.5	V		4
IDD	IDD		5.1	6.5	mA	Outputs unloaded, external reference	4
ISS	ISS		1	3	mA	Outputs unloaded	4
DICC	DICC		0.005	1	µA	VIH = DVCC, VIL = DGND	4
Settling Time, 20 V step			9	12.5	µs	20 V step to 1 LSB at 16-bit resolution	5
Settling Time, 10 V step			7.5	8.5	µs	10 V step to 1 LSB at 16-bit resolution	5
Zero-Scale TC, unipolar			5		µV/°C	Unipolar ranges, external reference	3
Zero-Scale TC, bipolar			15		µV/°C	Bipolar ranges, external reference	3
Gain Error TC			1.5		ppm FSR/°C	External reference	3
Output Voltage TC			3		ppm FSR/°C	±10 V range, external reference	4
Short-Circuit Current			25		mA	Short on the VOUT pin	4
Power Dissipation			67.1		mW	±11 V operation, outputs unloaded	4
SCLK cycle time	t1	20			ns		6
SCLK high time	t2	10			ns		6
SCLK low time	t3	10			ns		6
SYNC falling edge to SCLK falling edge setup time	t4	15			ns		6
SCLK rising edge to SDO valid	t16			40	ns	CL_SDO = 15 pF	6
VDD to AGND	VDD	-0.3		34	V		8
VSS to AGND	VSS	-17		0.3	V		8
DVCC to DGND	DVCC	-0.3		7	V		8
VREFIN to DGND	VREFIN	-0.3		7	V		8
Operating Temperature Range	TA	-40		125	°C	Industrial	8
Storage Temperature Range		-65		150	°C		8
Junction Temperature	TJ MAX			150	°C		8
Thermal Impedance θJA, 16-Lead TSSOP	θJA		113		°C/W	JEDEC 2S2P test board, still air (0 m/sec airflow)	8
Thermal Impedance θJC, 16-Lead TSSOP	θJC		28		°C/W		8
ESD (Human Body Model)				4	kV		8

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
housing	Abs		ESD (Human Body Model) 4 kV Stresses at or above those listed under Absolute Maximum	8

CAD (KiCad official)

Symbol: AD5761BRUZ
Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
3D model: TSSOP-16 (KiCad packages3D, STEP)
3D model files: ad5761bruz-etched.step / ad5761bruz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5761bruz.step / ad5761bruz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (31 pp, sha256 5df86567a5eabe16, retrieved 2026-10-31, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

AD5761BRUZ

Verified AD5761BRUZ

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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