component
AD5755ACPZ
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Analog Devices Digital To Analog Converters (DACs), LFCSP-64(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownAD5755ACPZ
Analog Devices · Digital To Analog Converters (DACs) · LFCSP-64(9x9)
AD5755ACPZ from Analog Devices, in a LFCSP-64(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RSET_B | passive | An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the IOUT_B temperature drift performance. |
| 2 | RSET_A | passive | An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the IOUT_A temperature drift performance. |
| 3 | REFGND | power_in | Ground reference point for the internal reference. |
| 4 | REFGND | power_in | Ground reference point for the internal reference. |
| 5 | AD0 | input | Address decode for the device under test on the board. |
| 6 | AD1 | input | Address decode for the device under test on the board; it is not recommended to tie both AD1 and AD0 low when using PEC. |
| 7 | SYNC | input | Active low frame synchronization input for the serial interface; data is transferred in on the falling edge of SCLK while SYNC is low. |
| 8 | SCLK | input | Serial clock input; data is clocked into the input shift register on the falling edge, at clock speeds of up to 30 MHz. |
| 9 | SDIN | input | Serial data input; data must be valid on the falling edge of SCLK. |
| 10 | SDO | output | Serial data output used to clock data from the serial register in readback mode. |
| 11 | DVDD | power_in | Digital supply with a voltage range from 2.7 V to 5.5 V. |
| 12 | DGND | power_in | Digital ground. |
| 13 | LDAC | input | Active low load DAC input that updates the DAC outputs; it must not be left unconnected. |
| 14 | CLEAR | input | Active high, edge sensitive input that sets the output current and voltage to the preprogrammed clear code; the DAC output register cannot be written while CLEAR is active. |
| 15 | ALERT | output | Active high output asserted when there has been no SPI activity on the interface pins for a predetermined time. |
| 16 | FAULT | output | Active low, open-drain output asserted on an open circuit in current mode, a short circuit in voltage mode, a PEC error, or an overtemperature. |
| 17 | POC | input | Power-on condition pin read during power-on or after a device reset; POC = 0 powers up the voltage and current channels in tristate, POC = 1 powers up the voltage channel with a 30 kΩ pull-down to ground. |
| 18 | RESET | input | Active low hardware reset input. |
| 19 | AVDD | power_in | Positive analog supply with a voltage range from 9 V to 33 V. |
| 20 | COMPLV_A | passive | Optional compensation capacitor connection for the VOUT_A output buffer; a 220 pF capacitor to VOUT_A allows the voltage output to drive up to 2 µF at the cost of increased settling time. |
| 21 | -VSENSE_A | input | Sense connection for the negative voltage output load of VOUT_A, which must stay within ±3.0 V of AGND for specified operation. |
| 22 | +VSENSE_A | input | Sense connection for the positive voltage output load of VOUT_A. |
| 23 | COMPDCDC_A | passive | DC-to-DC compensation capacitor for the Channel A converter, where a 10 nF capacitor is connected from this pin to ground. |
| 24 | VBOOST_A | power_in | Supply for the Channel A current output stage, which is also the supply for the VOUT_x stage regulated to 15 V by the dc-to-dc converter. |
| 25 | VOUT_A | output | Buffered analog output voltage for DAC Channel A. |
| 26 | IOUT_A | output | Current output pin for DAC Channel A. |
| 27 | AVSS | power_in | Negative analog supply with a voltage range from −10.8 V to −26.4 V. |
| 28 | COMPLV_B | passive | Optional compensation capacitor connection for the VOUT_B output buffer; a 220 pF capacitor to VOUT_B allows the voltage output to drive up to 2 µF at the cost of increased settling time. |
| 29 | -VSENSE_B | input | Sense connection for the negative voltage output load of VOUT_B, which must stay within ±3.0 V of AGND for specified operation. |
| 30 | +VSENSE_B | input | Sense connection for the positive voltage output load of VOUT_B. |
| 31 | VOUT_B | output | Buffered analog output voltage for DAC Channel B. |
| 32 | COMPDCDC_B | passive | DC-to-DC compensation capacitor for the Channel B converter, where a 10 nF capacitor is connected from this pin to ground. |
| 33 | IOUT_B | output | Current output pin for DAC Channel B. |
| 34 | VBOOST_B | power_in | Supply for the Channel B current output stage, which is also the supply for the VOUT_x stage regulated to 15 V by the dc-to-dc converter. |
| 35 | AGND | power_in | Ground reference point for analog circuitry, which must be connected to 0 V. |
| 36 | SWB | output | Switching output for the Channel B dc-to-dc circuitry. |
| 37 | GNDSWB | power_in | Ground connection for the Channel B dc-to-dc switching circuit, which should always be connected to ground. |
| 38 | GNDSWA | power_in | Ground connection for the Channel A dc-to-dc switching circuit, which should always be connected to ground. |
| 39 | SWA | output | Switching output for the Channel A dc-to-dc circuitry. |
| 40 | AVSS | power_in | Negative analog supply with a voltage range from −10.8 V to −26.4 V. |
| 41 | SWD | output | Switching output for the Channel D dc-to-dc circuitry. |
| 42 | GNDSWD | power_in | Ground connection for the Channel D dc-to-dc switching circuit, which should always be connected to ground. |
| 43 | GNDSWC | power_in | Ground connection for the Channel C dc-to-dc switching circuit, which should always be connected to ground. |
| 44 | SWC | output | Switching output for the Channel C dc-to-dc circuitry. |
| 45 | AVCC | power_in | Supply for the dc-to-dc circuitry. |
| 46 | VBOOST_C | power_in | Supply for the Channel C current output stage, which is also the supply for the VOUT_x stage regulated to 15 V by the dc-to-dc converter. |
| 47 | IOUT_C | output | Current output pin for DAC Channel C. |
| 48 | COMPDCDC_C | passive | DC-to-DC compensation capacitor for the Channel C converter, where a 10 nF capacitor is connected from this pin to ground. |
| 49 | VOUT_C | output | Buffered analog output voltage for DAC Channel C. |
| 50 | +VSENSE_C | input | Sense connection for the positive voltage output load of VOUT_C. |
| 51 | -VSENSE_C | input | Sense connection for the negative voltage output load of VOUT_C, which must stay within ±3.0 V of AGND for specified operation. |
| 52 | COMPLV_C | passive | Optional compensation capacitor connection for the VOUT_C output buffer; a 220 pF capacitor to VOUT_C allows the voltage output to drive up to 2 µF at the cost of increased settling time. |
| 53 | AVSS | power_in | Negative analog supply pin. |
| 54 | IOUT_D | output | Current output pin for DAC Channel D. |
| 55 | VOUT_D | output | Buffered analog output voltage for DAC Channel D. |
| 56 | VBOOST_D | power_in | Supply for the Channel D current output stage, which is also the supply for the VOUT_x stage regulated to 15 V by the dc-to-dc converter. |
| 57 | COMPDCDC_D | passive | DC-to-DC compensation capacitor for the Channel D converter, where a 10 nF capacitor is connected from this pin to ground. |
| 58 | +VSENSE_D | input | Sense connection for the positive voltage output load of VOUT_D. |
| 59 | -VSENSE_D | input | Sense connection for the negative voltage output load of VOUT_D, which must stay within ±3.0 V of AGND for specified operation. |
| 60 | COMPLV_D | passive | Optional compensation capacitor connection for the VOUT_D output buffer; a 220 pF capacitor to VOUT_D allows the voltage output to drive up to 2 µF at the cost of increased settling time. |
| 61 | REFIN | input | External reference voltage input. |
| 62 | REFOUT | output | Internal reference voltage output; it is recommended to place a 0.1 µF capacitor between REFOUT and REFGND. |
| 63 | RSET_D | passive | An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the IOUT_D temperature drift performance. |
| 64 | RSET_C | passive | An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the IOUT_C temperature drift performance. |
| 65 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LFCSP-64(9x9) |
| Category | ADC/DAC/Data Conversion |
| Pins | 65 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Total Unadjusted Error (TUE) | TUE | -0.25 | 0.25 | % FSR | A Version; AVSS = −15 V, loaded and unloaded | 4 | |
| Total Unadjusted Error (TUE) | TUE | -0.075 | 0.02 | 0.075 | % FSR | A Version; TA = 25°C | 4 |
| Relative Accuracy (INL) | INL | -0.006 | 0.0012 | 0.006 | % FSR | 0 V to 5 V, 0 V to 10 V, ±5 V, ±10 V ranges | 4 |
| Differential Nonlinearity (DNL) | DNL | -1 | 1 | LSB | Guaranteed monotonic | 4 | |
| Zero-Scale Error | -0.03 | 0.002 | 0.03 | % FSR | 4 | ||
| Zero-Scale TC | -2 | 2 | ppm FSR/°C | 4 | |||
| Bipolar Zero Error | -0.03 | 0.002 | 0.03 | % FSR | 4 | ||
| Bipolar Zero TC | -1 | 1 | ppm FSR/°C | 4 | |||
| Offset Error | -0.03 | 0.002 | 0.03 | % FSR | 4 | ||
| Offset TC | -2 | 2 | ppm FSR/°C | 4 | |||
| Gain Error | -0.03 | 0.004 | 0.03 | % FSR | 4 | ||
| Gain TC | -3 | 3 | ppm FSR/°C | 4 | |||
| Full-Scale Error | -0.03 | 0.002 | 0.03 | % FSR | 4 | ||
| Full-Scale TC | -2 | 2 | ppm FSR/°C | 4 | |||
| Total Unadjusted Error (TUE) | TUE | -0.2 | 0.04 | 0.2 | % FSR | A Version; External RSET | 5 |
| Relative Accuracy (INL) | INL | -0.006 | 0.006 | % FSR | External RSET | 5 | |
| Offset Error | -0.05 | 0.005 | 0.05 | % FSR | External RSET | 5 | |
| Offset Error Drift | -4 | 4 | ppm FSR/°C | External RSET | 5 | ||
| Gain Error | -0.05 | 0.004 | 0.05 | % FSR | External RSET | 5 | |
| Gain TC | -3 | 3 | ppm FSR/°C | External RSET | 5 | ||
| Full-Scale Error | -0.05 | 0.008 | 0.05 | % FSR | External RSET | 5 | |
| Full-Scale TC | -5 | 5 | ppm FSR/°C | External RSET | 5 | ||
| Total Unadjusted Error (TUE) | TUE | -0.35 | 0.35 | % FSR | A Version; Internal RSET | 5 | |
| Offset Error | -0.05 | 0.05 | % FSR | Internal RSET | 5 | ||
| Offset Error Drift | -6 | 6 | ppm FSR/°C | Internal RSET | 5 | ||
| Gain Error | -0.12 | 0.12 | % FSR | Internal RSET | 5 | ||
| Gain TC | -9 | 9 | ppm FSR/°C | Internal RSET | 5 | ||
| Full-Scale Error | -0.14 | 0.14 | % FSR | Internal RSET | 5 | ||
| Full-Scale TC | -14 | 14 | ppm FSR/°C | Internal RSET | 5 | ||
| Reference Input Voltage | REFIN | 4.95 | 5 | 5.05 | V | For specified performance | 6 |
| DC Input Impedance | 45 | 150 | MΩ | 6 | |||
| Reference Output Voltage | REFOUT | 4.995 | 5 | 5.005 | V | TA = 25°C | 6 |
| Reference TC | -10 | 5 | 10 | ppm/°C | 6 | ||
| Oscillator Frequency | 11.5 | 13 | 14.5 | MHz | This oscillator is divided down to give the dc-to-dc converter switching frequency | 6 | |
| VIH, Input High Voltage | VIH | 2 | V | JEDEC compliant | 6 | ||
| VIL, Input Low Voltage | VIL | 0.8 | V | JEDEC compliant | 6 | ||
| Input Current | -1 | 1 | µA | Per pin | 6 | ||
| VOL, Output Low Voltage (SDO, ALERT) | VOL | 0.4 | V | Sinking 200 µA | 6 | ||
| AVDD | AVDD | 9 | 33 | V | 6 | ||
| AVSS | AVSS | -26.4 | -10.8 | V | 6 | ||
| DVDD | DVDD | 2.7 | 5.5 | V | 6 | ||
| AVCC | AVCC | 4.5 | 5.5 | V | 6 | ||
| AIDD | AIDD | 8.6 | 10.5 | mA | Voltage output mode on all channels, output unloaded, over supplies | 6 | |
| AISS | AISS | -11 | -8.8 | mA | Voltage output mode on all channels, output unloaded, over supplies | 6 | |
| DICC | DICC | 9.2 | 11 | mA | VIH = DVDD, VIL = DGND, internal oscillator running, over supplies | 7 | |
| AVDD, VBOOST_x to AGND, DGND | AVDD, VBOOST_x | -0.3 | 33 | V | TA = 25°C, unless otherwise noted | 11 | |
| AVSS to AGND, DGND | AVSS | -28 | 0.3 | V | TA = 25°C, unless otherwise noted | 11 | |
| AVDD to AVSS | AVDD, AVSS | -0.3 | 60 | V | TA = 25°C, unless otherwise noted | 11 | |
| AVCC to AGND | AVCC | -0.3 | 7 | V | TA = 25°C, unless otherwise noted | 11 | |
| DVDD to DGND | DVDD | -0.3 | 7 | V | TA = 25°C, unless otherwise noted | 11 | |
| Digital Inputs to DGND | -0.3 | V | Max is DVDD + 0.3 V or +7 V, whichever is less | 11 | |||
| Digital Outputs to DGND | -0.3 | V | Max is DVDD + 0.3 V or +7 V, whichever is less | 11 | |||
| REFIN, REFOUT to AGND | REFIN, REFOUT | -0.3 | V | Max is AVDD + 0.3 V or +7 V, whichever is less | 11 | ||
| SWx to AGND | SWx | -0.3 | 33 | V | TA = 25°C, unless otherwise noted | 11 | |
| AGND, GNDSWx to DGND | AGND, GNDSWx | -0.3 | 0.3 | V | TA = 25°C, unless otherwise noted | 11 | |
| Operating Temperature Range (TA), Industrial | TA | -40 | 105 | °C | 11 | ||
| Junction Temperature (TJ max) | TJ | 125 | °C | 11 | |||
| θJA Thermal Impedance | θJA | 28 | °C/W | 64-Lead LFCSP, based on JEDEC 4-layer test board | 11 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | EPAD Exposed Pad. This exposed pad should be connected to the potential of the AVSS pin, or, alternatively, it can be left electrically unconnected. It is recommended that the pad be thermally connect | 14 |
CAD (KiCad official)
- Symbol:
AD5755ACPZ - Footprint:
Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm - 3D model: LFCSP-64(9x9) (KiCad packages3D, STEP)
- 3D model files:
ad5755acpz-etched.step/ad5755acpz-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad5755acpz.step/ad5755acpz.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (50 pp, sha256
ab1187019b9c588e, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).