AD5689RBCPZ-RL7

{
  "schema_version": 1,
  "type": "component",
  "slug": "ad5689rbcpz-rl7",
  "title": "AD5689RBCPZ-RL7",
  "brief": "Analog Devices Digital To Analog Converters (DACs), LFCSP-16(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
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    "data converters",
    "ad5689rbcpz-rl7",
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  "component": {
    "mpn": "AD5689RBCPZ-RL7",
    "manufacturer": "Analog Devices",
    "package": "LFCSP-16(3x3)",
    "pin_count": 17,
    "category": "Data Converters",
    "subcategory": "Digital To Analog Converters (DACs)",
    "datasheet": "https://www.analog.com/media/en/technical-documentation/data-sheets/AD5689R_5687R.pdf",
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    "distributor_links": {
      "lcsc": "C488310",
      "digikey": "505-AD5689RBCPZ-RL7TR-ND",
      "mouser": "584-AD5689RBCPZ-R7"
    },
    "distributor_check": {
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      "source": "Component Ocean /api/assign-pns",
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      "mouser": {
        "pn": "584-AD5689RBCPZ-R7",
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        "lifecycle": "Restricted Availability"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "VOUTA",
        "type": "output",
        "description": "Analog output voltage from DAC A; the output amplifier has rail-to-rail operation."
      },
      {
        "number": "2",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference point for all circuitry on the AD5689R/AD5687R."
      },
      {
        "number": "3",
        "name": "VDD",
        "type": "power_in",
        "description": "Power supply input that operates from 2.7 V to 5.5 V and should be decoupled with 10 µF in parallel with 0.1 µF to GND."
      },
      {
        "number": "4",
        "name": "NC",
        "type": "unconnected",
        "description": "No connect; do not connect to this pin."
      },
      {
        "number": "5",
        "name": "VOUTB",
        "type": "output",
        "description": "Analog output voltage from DAC B; the output amplifier has rail-to-rail operation."
      },
      {
        "number": "6",
        "name": "SDO",
        "type": "output",
        "description": "Serial data output used to daisy-chain multiple devices or for readback, with data transferred on the SCLK rising edge and valid on the falling edge."
      },
      {
        "number": "7",
        "name": "LDAC",
        "type": "input",
        "description": "Load DAC control that, when pulsed low, updates either or both DAC registers from their input registers; the pin can also be tied permanently low."
      },
      {
        "number": "8",
        "name": "GAIN",
        "type": "input",
        "description": "Gain select: tying this pin to GND gives a 0 V to VREF output span, and tying it to VLOGIC gives a 0 V to 2 × VREF span."
      },
      {
        "number": "9",
        "name": "VLOGIC",
        "type": "power_in",
        "description": "Digital power supply with a voltage range of 1.62 V to 5.5 V."
      },
      {
        "number": "10",
        "name": "SCLK",
        "type": "input",
        "description": "Serial clock input that clocks data into the input shift register on the falling edge at rates up to 50 MHz."
      },
      {
        "number": "11",
        "name": "SYNC",
        "type": "input",
        "description": "Active-low frame synchronization input; when SYNC goes low, data is transferred in on the falling edges of the next 24 clocks."
      },
      {
        "number": "12",
        "name": "SDIN",
        "type": "input",
        "description": "Serial data input to a 24-bit input shift register, clocked in on the falling edge of SCLK."
      },
      {
        "number": "13",
        "name": "RESET",
        "type": "input",
        "description": "Asynchronous, falling-edge-sensitive reset input that sets the outputs to zero scale or midscale per RSTSEL, and LDAC pulses are ignored while it is low."
      },
      {
        "number": "14",
        "name": "RSTSEL",
        "type": "input",
        "description": "Power-on reset select: tying this pin to GND powers both DACs up to zero scale, and tying it to VLOGIC powers them up to midscale."
      },
      {
        "number": "15",
        "name": "VREF",
        "type": "power_in",
        "description": "Common reference pin that is a reference output by default when using the internal reference and a reference input when using an external reference."
      },
      {
        "number": "16",
        "name": "NC",
        "type": "unconnected",
        "description": "No connect; do not connect to this pin."
      },
      {
        "number": "17",
        "name": "EPAD",
        "type": "passive",
        "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
      }
    ],
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        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The exposed pad must be tied to GND (Figure 6 note 1 and Table 7), but it has no printed pin number ; Figure 6 pin labels are garbled in the text extraction; the pin-to-name mapping was taken from Table",
          "exposed pad 17 added from the footprint"
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        "pages_sent": 12,
        "cost_usd": 0.0798,
        "at": "2026-10-29T01:47:09"
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        "pages": 28,
        "sha256": "76599fb4ebf80e89",
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      "cad": "KiCad official (CC-BY-SA 4.0)",
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        "described": 17,
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  "metadata": {
    "specs": {
      "Manufacturer": "Analog Devices",
      "Package": "LFCSP-16(3x3)",
      "Category": "Data Converters",
      "Pins": "17"
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          "name": "Reflow Soldering Peak Temperature, Pb Free",
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          "name": "DC Power Supply Rejection Ratio",
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          "name": "Output Voltage Settling Time, AD5689R",
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        {
          "name": "SYNC to SCLK Falling Edge Setup Time",
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