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AD5689RBCPZ-RL7

Analog Devices · Digital To Analog Converters (DACs) · LFCSP-16(3x3)

AD5689RBCPZ-RL7 from Analog Devices, in a LFCSP-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VOUTA	output	Analog output voltage from DAC A; the output amplifier has rail-to-rail operation.
2	GND	power_in	Ground reference point for all circuitry on the AD5689R/AD5687R.
3	VDD	power_in	Power supply input that operates from 2.7 V to 5.5 V and should be decoupled with 10 µF in parallel with 0.1 µF to GND.
4	NC	unconnected	No connect; do not connect to this pin.
5	VOUTB	output	Analog output voltage from DAC B; the output amplifier has rail-to-rail operation.
6	SDO	output	Serial data output used to daisy-chain multiple devices or for readback, with data transferred on the SCLK rising edge and valid on the falling edge.
7	LDAC	input	Load DAC control that, when pulsed low, updates either or both DAC registers from their input registers; the pin can also be tied permanently low.
8	GAIN	input	Gain select: tying this pin to GND gives a 0 V to VREF output span, and tying it to VLOGIC gives a 0 V to 2 × VREF span.
9	VLOGIC	power_in	Digital power supply with a voltage range of 1.62 V to 5.5 V.
10	SCLK	input	Serial clock input that clocks data into the input shift register on the falling edge at rates up to 50 MHz.
11	SYNC	input	Active-low frame synchronization input; when SYNC goes low, data is transferred in on the falling edges of the next 24 clocks.
12	SDIN	input	Serial data input to a 24-bit input shift register, clocked in on the falling edge of SCLK.
13	RESET	input	Asynchronous, falling-edge-sensitive reset input that sets the outputs to zero scale or midscale per RSTSEL, and LDAC pulses are ignored while it is low.
14	RSTSEL	input	Power-on reset select: tying this pin to GND powers both DACs up to zero scale, and tying it to VLOGIC powers them up to midscale.
15	VREF	power_in	Common reference pin that is a reference output by default when using the internal reference and a reference input when using an external reference.
16	NC	unconnected	No connect; do not connect to this pin.
17	EPAD	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	LFCSP-16(3x3)
Category	Data Converters
Pins	17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
VDD to GND	VDD	-0.3		7	V		9
VLOGIC to GND	VLOGIC	-0.3		7	V		9
Operating Temperature Range		-40		105	°C		9
Storage Temperature Range		-65		150	°C		9
Junction Temperature				125	°C		9
Reflow Soldering Peak Temperature, Pb Free				260	°C	J-STD-020	9
Relative Accuracy (INL), B grade		-2	1	2	LSB	Gain = 2	3
Relative Accuracy (INL), B grade		-3	1	3	LSB	Gain = 1	3
Differential Nonlinearity		-1		1	LSB	Guaranteed monotonic by design	3
Zero-Code Error			0.4	1.5	mV	All 0s loaded to DAC register	3
Offset Error		-1.5	0.1	1.5	mV		3
Full-Scale Error		-0.1	0.01	0.1	% of FSR	All 1s loaded to DAC register	3
Gain Error		-0.1	0.02	0.1	% of FSR		3
Offset Error Drift		-1		1	µV/°C		3
Gain Temperature Coefficient		-1		1	ppm Of FSR/°C		3
DC Power Supply Rejection Ratio				0.15	mV/V	DAC code = midscale; VDD = 5 V ± 10%	3
DC Crosstalk due to single channel full-scale output change		-2		2	µV	Due to single channel, full-scale output change	3
DC Crosstalk due to load current change		-3		3	µV/mA	Due to load current change	3
DC Crosstalk due to powering down (per channel)		-2		2	µV	Due to powering down (per channel)	3
Output Voltage Range, gain = 1	VOUT	0			V	Gain = 1	3
Output Voltage Range, gain = 2	VOUT	0			V	Gain = 2, see Figure 31	3
Capacitive Load Stability				2	nF	RL = ∞	3
Capacitive Load Stability				10	nF	RL = 1 kΩ	3
Resistive Load		1			kΩ		3
Load Regulation				80	µV/mA	5 V ± 10%, DAC code = midscale; −30 mA ≤ IOUT ≤ 30 mA	3
Short-Circuit Current				40	mA	VDD = 5 V	3
Power-Up Time				2.5	µs	Coming out of power-down mode; VDD = 5 V	3
Output Voltage		2.4975		2.5025	V	At ambient	4
Reference Temperature Coefficient			2	5	ppm/°C		4
Input Current		-2		2	µA	Per pin	4
Logic Output Low Voltage (VOL)	VOL			0.4	V	ISINK = 200 μA	4
VLOGIC	VLOGIC	1.62		5.5	V		4
Logic Supply Current	ILOGIC			3	µA		4
VDD	VDD	2.7		5.5	V	Gain = 1	4
VDD	VDD			5.5	V	Gain = 2	4
Normal Mode supply current, internal reference off	IDD		0.59	0.7	mA	VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V; internal reference off	4
Normal Mode supply current, internal reference on at full scale	IDD		1.1	1.3	mA	Internal reference on, at full scale; VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V	4
All Power-Down Modes supply current	IDD		1	4	µA	−40°C to +85°C	4
All Power-Down Modes supply current	IDD			6	µA	−40°C to +105°C	4
Output Voltage Settling Time, AD5689R			5	8	µs	¼ to ¾ scale settling to ±2 LSB	5
SCLK Cycle Time	t1	20			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
SCLK High Time	t2	10			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
SCLK Low Time	t3	10			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
SYNC to SCLK Falling Edge Setup Time	t4	10			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
Data Setup Time	t5	5			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
Data Hold Time	t6	5			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
SCLK Falling Edge to SYNC Rising Edge	t7	10			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
Minimum SYNC High Time	t8	20			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
SYNC Rising Edge to SYNC Rising Edge (DAC Register Updates)	t9	830			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
SYNC Falling Edge to SCLK Fall Ignore	t10	10			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
LDAC Pulse Width Low	t11	15			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
SYNC Rising Edge to LDAC Rising Edge	t12	20			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
SYNC Rising Edge to LDAC Falling Edge	t13	30			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
LDAC Falling Edge to SYNC Rising Edge	t14	800			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
Minimum Pulse Width Low	t15	30			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
Pulse Activation Time	t16	30			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
Power-Up Time (exit power-down to normal mode)		4.5			µs	2.7 V ≤ VLOGIC ≤ 5.5 V; SYNC rising edge to 90% of DAC midscale, output unloaded	6
16-Lead LFCSP θJA Thermal Impedance, 0 Airflow (4-Layer Board)	θJA		70		°C/W	0 airflow (4-layer board)	9

CAD (KiCad official)

Symbol: AD5689RBCPZ-RL7
Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
3D model: LFCSP-16(3x3) (KiCad packages3D, STEP)
3D model files: ad5689rbcpz-rl7-etched.step / ad5689rbcpz-rl7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5689rbcpz-rl7.step / ad5689rbcpz-rl7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (28 pp, sha256 76599fb4ebf80e89, retrieved 2026-10-29, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF