AD5686RBRUZ-RL7

{
  "slug": "ad5686rbruz-rl7",
  "version": "0.1.0",
  "type": "component",
  "description": "Analog Devices Digital To Analog Converters (DAC), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "data acquisition",
    "ad5686rbruz-rl7",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
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    "type": "image",
    "path": "docs/hero.png"
  },
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    "README.md",
    "ad5686rbruz-rl7.kicad_sym",
    "ad5686rbruz-rl7.kicad_mod",
    "ad5686rbruz-rl7.glb",
    "ad5686rbruz-rl7.step",
    "ad5686rbruz-rl7.lbr",
    "docs/hero.png",
    "docs/ad5686rbruz-rl7-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "ad5686rbruz-rl7-hero.glb",
    "ad5686rbruz-rl7-hero.overlay.json",
    "ad5686rbruz-rl7-etched.glb"
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  "component": {
    "mpn": "AD5686RBRUZ-RL7",
    "manufacturer": "Analog Devices",
    "package": "TSSOP-16",
    "pin_count": 16,
    "category": "Data Acquisition",
    "subcategory": "Digital To Analog Converters (DAC)",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588940286995546112",
    "parts": {
      "symbol": "ad5686rbruz-rl7.kicad_sym",
      "footprint": "ad5686rbruz-rl7.kicad_mod",
      "model_3d": "ad5686rbruz-rl7-hero.glb",
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      "model_3d_step": "ad5686rbruz-rl7-etched.step",
      "model_3d_step_plain": "ad5686rbruz-rl7.step",
      "lbr": "ad5686rbruz-rl7.lbr"
    },
    "distributor_links": {
      "lcsc": "C650110",
      "digikey": "AD5686RBRUZ-RL7TR-ND",
      "mouser": "584-AD5686RBRUZ-R7"
    },
    "distributor_check": {
      "checked_at": "2026-10-20T23:41:24Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "AD5686RBRUZ-RL7TR-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "584-AD5686RBRUZ-R7",
        "status": "found",
        "lifecycle": "Restricted Availability"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "VREF",
        "type": "power_in",
        "description": "Reference voltage pin: it is the output of the internal 2.5 V reference by default, or the input when an external reference is used."
      },
      {
        "number": "2",
        "name": "VOUTB",
        "type": "output",
        "description": "Analog output voltage from DAC B; the output amplifier has rail-to-rail operation."
      },
      {
        "number": "3",
        "name": "VOUTA",
        "type": "output",
        "description": "Analog output voltage from DAC A; the output amplifier has rail-to-rail operation."
      },
      {
        "number": "4",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference point for all circuitry on the part."
      },
      {
        "number": "5",
        "name": "VDD",
        "type": "power_in",
        "description": "Power supply input operable from 2.7 V to 5.5 V, to be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND."
      },
      {
        "number": "6",
        "name": "VOUTC",
        "type": "output",
        "description": "Analog output voltage from DAC C; the output amplifier has rail-to-rail operation."
      },
      {
        "number": "7",
        "name": "VOUTD",
        "type": "output",
        "description": "Analog output voltage from DAC D; the output amplifier has rail-to-rail operation."
      },
      {
        "number": "8",
        "name": "SDO",
        "type": "output",
        "description": "Serial data output used for daisy-chaining or readback; data is transferred on the rising edge of SCLK and is valid on the falling edge."
      },
      {
        "number": "9",
        "name": "LDAC",
        "type": "input",
        "description": "Load DAC input operating asynchronously or synchronously; pulsing low updates any or all DAC registers that hold new input data, and the pin can be tied permanently low."
      },
      {
        "number": "10",
        "name": "GAIN",
        "type": "input",
        "description": "Span select pin: tied to GND gives a 0 V to VREF output span, and tied to VLOGIC gives a 0 V to 2 × VREF span."
      },
      {
        "number": "11",
        "name": "VLOGIC",
        "type": "power_in",
        "description": "Digital power supply with a voltage range of 1.8 V to 5.5 V."
      },
      {
        "number": "12",
        "name": "SCLK",
        "type": "input",
        "description": "Serial clock input; data is clocked into the input shift register on the falling edge at rates up to 50 MHz."
      },
      {
        "number": "13",
        "name": "SYNC",
        "type": "input",
        "description": "Active-low frame synchronization input; when it goes low, data is transferred in on the falling edges of the next 24 clocks."
      },
      {
        "number": "14",
        "name": "SDIN",
        "type": "input",
        "description": "Serial data input to the 24-bit input shift register, clocked in on the falling edge of SCLK."
      },
      {
        "number": "15",
        "name": "RESET",
        "type": "input",
        "description": "Asynchronous, falling-edge-sensitive reset input that loads the input and DAC registers with zero scale or midscale per RSTSEL; if held low at power-up the POR circuit does not initialize correctly until released."
      },
      {
        "number": "16",
        "name": "RSTSEL",
        "type": "input",
        "description": "Power-on reset select: tying it to GND powers all four DACs up to zero scale, and tying it to VLOGIC powers them up to midscale."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Pin numbering conflict within the datasheet. The TSSOP column of Table 7 (page 10) gives VREF=1, VOU; Pin names in the extracted text for LDAC, SYNC and RESET are garbled with overbar artifacts (ALDACE,"
        ],
        "pages_sent": 9,
        "cost_usd": 0.0609,
        "at": "2026-10-20T23:37:46"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588940286995546112",
        "pages": 31,
        "sha256": "ec441b37f028d60d",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
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      "footprint": "viewers/footprint.html"
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        "zmin_mm": -0.0,
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        "sha256": "6ad5e98224d02a427d9a6b929a28dbc158b9925fba5adec12db05079f1016948",
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        "sha256": "8e348998dab693081e6f322ebd815076e1144e1a93bc84acc451e69637341662",
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}