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AD5686RBRUZ-RL7

Analog Devices · Digital To Analog Converters (DAC) · TSSOP-16

AD5686RBRUZ-RL7 from Analog Devices, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VREF	power_in	Reference voltage pin: it is the output of the internal 2.5 V reference by default, or the input when an external reference is used.
2	VOUTB	output	Analog output voltage from DAC B; the output amplifier has rail-to-rail operation.
3	VOUTA	output	Analog output voltage from DAC A; the output amplifier has rail-to-rail operation.
4	GND	power_in	Ground reference point for all circuitry on the part.
5	VDD	power_in	Power supply input operable from 2.7 V to 5.5 V, to be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
6	VOUTC	output	Analog output voltage from DAC C; the output amplifier has rail-to-rail operation.
7	VOUTD	output	Analog output voltage from DAC D; the output amplifier has rail-to-rail operation.
8	SDO	output	Serial data output used for daisy-chaining or readback; data is transferred on the rising edge of SCLK and is valid on the falling edge.
9	LDAC	input	Load DAC input operating asynchronously or synchronously; pulsing low updates any or all DAC registers that hold new input data, and the pin can be tied permanently low.
10	GAIN	input	Span select pin: tied to GND gives a 0 V to VREF output span, and tied to VLOGIC gives a 0 V to 2 × VREF span.
11	VLOGIC	power_in	Digital power supply with a voltage range of 1.8 V to 5.5 V.
12	SCLK	input	Serial clock input; data is clocked into the input shift register on the falling edge at rates up to 50 MHz.
13	SYNC	input	Active-low frame synchronization input; when it goes low, data is transferred in on the falling edges of the next 24 clocks.
14	SDIN	input	Serial data input to the 24-bit input shift register, clocked in on the falling edge of SCLK.
15	RESET	input	Asynchronous, falling-edge-sensitive reset input that loads the input and DAC registers with zero scale or midscale per RSTSEL; if held low at power-up the POR circuit does not initialize correctly until released.
16	RSTSEL	input	Power-on reset select: tying it to GND powers all four DACs up to zero scale, and tying it to VLOGIC powers them up to midscale.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	TSSOP-16
Category	Data Acquisition
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Relative Accuracy (INL), AD5686R, gain = 2		-2	1	2	LSB	Gain = 2	3
Relative Accuracy (INL), AD5686R, gain = 1		-3	1	3	LSB	Gain = 1	3
Relative Accuracy (INL), AD5685R		-1	0.5	1	LSB		3
Relative Accuracy (INL), AD5684R		-1	0.12	1	LSB		3
Differential Nonlinearity, AD5686R		-1		1	LSB	Guaranteed monotonic by design	3
Differential Nonlinearity, AD5685R		-1		1	LSB	Guaranteed monotonic by design	3
Differential Nonlinearity, AD5684R		-1		1	LSB	Guaranteed monotonic by design	3
Zero-Code Error			0.4	1.5	mV	All zeros loaded to DAC register	3
Offset Error		-1.5	0.1	1.5	mV		3
Full-Scale Error		-0.1	0.01	0.1	% of FSR	All ones loaded to DAC register	3
Gain Error		-0.1	0.02	0.1	% of FSR		3
Total Unadjusted Error		-0.1	0.01	0.1	% of FSR	External reference; gain = 2; TSSOP	3
Total Unadjusted Error		-0.2		0.2	% of FSR	Internal reference; gain = 1; TSSOP	3
Output Voltage Range, gain = 1		0			V	Gain = 1	3
Output Voltage Range, gain = 2		0			V	Gain = 2; see Figure 33	3
Capacitive Load Stability				2	nF	RL = ∞	3
Capacitive Load Stability				10	nF	RL = 1 kΩ	3
Resistive Load		1			kΩ		3
Short-Circuit Current				40	mA	VDD = 5 V	3
Load Regulation				80	µV/mA	5 V ± 10%, DAC code = midscale; −30 mA ≤ IOUT ≤ 30 mA	3
Output Voltage (internal reference)		2.4975		2.5025	V	At ambient	4
Reference TC			2	5	ppm/°C	See the Terminology section	4
Output Current Load Capability		-5		5	mA	VDD ≥ 3 V	4
Input Current		-2		2	µA	Per pin	4
Pin Capacitance				2	pF		4
Output Low Voltage (SDO)	VOL			0.4	V	ISINK = 200 μA	4
Floating State Output Capacitance (SDO)				4	pF		4
VLOGIC Supply Voltage	VLOGIC	1.62		5.5	V		4
Logic Supply Current	ILOGIC			3	µA		4
VDD Supply Voltage	VDD	2.7		5.5	V	Gain = 1	4
VDD Supply Voltage	VDD			5.5	V	Gain = 2 (minimum is VREF + 1.5 V)	4
Normal Mode Supply Current, internal reference off	IDD		0.59	0.7	mA	VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V; internal reference off	4
Normal Mode Supply Current, internal reference on, full scale	IDD		1.1	1.3	mA	VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V; internal reference on, at full scale	4
All Power-Down Modes Supply Current	IDD		1	4	µA	−40°C to +85°C	4
All Power-Down Modes Supply Current	IDD			6	µA	−40°C to +105°C	4
VDD to GND	VDD	-0.3		7	V		9
VLOGIC to GND	VLOGIC	-0.3		7	V		9
VOUT to GND	VOUT	-0.3			V	Max is VDD + 0.3 V	9
VREF to GND	VREF	-0.3			V	Max is VDD + 0.3 V	9
Digital Input Voltage to GND		-0.3			V	Max is VLOGIC + 0.3 V	9
Operating Temperature Range		-40		105	°C		9
Storage Temperature Range		-65		150	°C		9
Junction Temperature				125	°C		9
Reflow Soldering Peak Temperature				260	°C	Pb free (J-STD-020)	9
SCLK Cycle Time	t1	20			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
SCLK High Time	t2	10			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
SCLK Low Time	t3	10			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
SYNC to SCLK Falling Edge Setup Time	t4	10			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
Data Setup Time	t5	5			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
Data Hold Time	t6	5			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
SCLK Falling Edge to SYNC Rising Edge	t7	10			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
Minimum SYNC High Time	t8	20			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
SYNC Rising Edge to SYNC Rising Edge (DAC Register Updates)	t9	830			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
SYNC Falling Edge to SCLK Fall Ignore	t10	10			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
LDAC Pulse Width Low	t11	15			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
SYNC Rising Edge to LDAC Rising Edge	t12	20			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
SYNC Rising Edge to LDAC Falling Edge	t13	30			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
LDAC Falling Edge to SYNC Rising Edge	t14	800			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
Thermal Impedance, junction to ambient, 16-lead TSSOP	θJA		112.6		°C/W	0 airflow, 4-layer board	9

CAD (KiCad official)

Symbol: AD5686RBRUZ-RL7
Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
3D model: TSSOP-16 (KiCad packages3D, STEP)
3D model files: ad5686rbruz-rl7-etched.step / ad5686rbruz-rl7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5686rbruz-rl7.step / ad5686rbruz-rl7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (31 pp, sha256 ec441b37f028d60d, retrieved 2026-10-20, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF