AD5684RBRUZ

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  "slug": "ad5684rbruz",
  "title": "AD5684RBRUZ",
  "brief": "Analog Devices Digital To Analog Converters (DACs), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
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  "component": {
    "mpn": "AD5684RBRUZ",
    "manufacturer": "Analog Devices",
    "package": "TSSOP-16",
    "pin_count": 16,
    "category": "Data Converters",
    "subcategory": "Digital To Analog Converters (DACs)",
    "datasheet": "https://www.analog.com/media/en/technical-documentation/data-sheets/AD5686R_5685R_5684R.pdf",
    "parts": {
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      "model_3d_step_plain": "ad5684rbruz.step",
      "lbr": "ad5684rbruz.lbr"
    },
    "distributor_links": {
      "lcsc": "C578274",
      "digikey": "505-AD5684RBRUZ-ND",
      "mouser": "584-AD5684RBRUZ"
    },
    "distributor_check": {
      "checked_at": "2026-10-31T12:35:28Z",
      "source": "Component Ocean /api/assign-pns",
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        "pn": "505-AD5684RBRUZ-ND",
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        "pn": "584-AD5684RBRUZ",
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    },
    "pins": [
      {
        "number": "1",
        "name": "VREF",
        "type": "power_in",
        "description": "Common reference pin: reference output when using the internal reference (default) and reference input when using an external reference."
      },
      {
        "number": "2",
        "name": "VOUTB",
        "type": "output",
        "description": "Analog output voltage from DAC B with rail-to-rail output amplifier."
      },
      {
        "number": "3",
        "name": "VOUTA",
        "type": "output",
        "description": "Analog output voltage from DAC A with rail-to-rail output amplifier."
      },
      {
        "number": "4",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference point for all circuitry on the part."
      },
      {
        "number": "5",
        "name": "VDD",
        "type": "power_in",
        "description": "Power supply input, 2.7 V to 5.5 V, decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND."
      },
      {
        "number": "6",
        "name": "VOUTC",
        "type": "output",
        "description": "Analog output voltage from DAC C with rail-to-rail output amplifier."
      },
      {
        "number": "7",
        "name": "VOUTD",
        "type": "output",
        "description": "Analog output voltage from DAC D with rail-to-rail output amplifier."
      },
      {
        "number": "8",
        "name": "SDO",
        "type": "output",
        "description": "Serial data output used to daisy-chain devices or for readback; data transferred on the rising edge of SCLK and valid on the falling edge."
      },
      {
        "number": "9",
        "name": "LDAC",
        "type": "input",
        "description": "Load DAC input operated asynchronously or synchronously; pulsing low updates DAC registers simultaneously, and it can be tied permanently low."
      },
      {
        "number": "10",
        "name": "GAIN",
        "type": "input",
        "description": "Span set pin: tied to GND gives 0 V to VREF output span, tied to VLOGIC gives 0 V to 2 × VREF for all four DACs."
      },
      {
        "number": "11",
        "name": "VLOGIC",
        "type": "power_in",
        "description": "Digital power supply, 1.8 V to 5.5 V."
      },
      {
        "number": "12",
        "name": "SCLK",
        "type": "input",
        "description": "Serial clock input; data is clocked into the shift register on the falling edge at up to 50 MHz."
      },
      {
        "number": "13",
        "name": "SYNC",
        "type": "input",
        "description": "Active-low frame synchronization input; when low, data is transferred in on the falling edges of the next 24 clocks."
      },
      {
        "number": "14",
        "name": "SDIN",
        "type": "input",
        "description": "Serial data input to the 24-bit input shift register, clocked on the falling edge of SCLK."
      },
      {
        "number": "15",
        "name": "RESET",
        "type": "input",
        "description": "Asynchronous falling-edge-sensitive reset input; LDAC pulses are ignored while low and registers go to zero or midscale per RSTSEL."
      },
      {
        "number": "16",
        "name": "RSTSEL",
        "type": "input",
        "description": "Power-on reset select: tied to GND powers up all DACs to zero scale, tied to VLOGIC powers up to midscale."
      }
    ],
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        "guard_notes": [
          "extractor flagged: Pin types for VREF (bidirectional) and SDO (output) are inferred from the descriptions; the datashee"
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        "at": "2026-10-31T12:35:08"
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        "total": 16,
        "described": 16,
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  "metadata": {
    "specs": {
      "Manufacturer": "Analog Devices",
      "Package": "TSSOP-16",
      "Category": "Data Converters",
      "Pins": "16"
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          "name": "Reference Output Voltage Noise Density",
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          "min": null,
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          "name": "Reference Load Regulation Sourcing",
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          "name": "Reference Load Regulation Sinking",
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          "name": "Reference Line Regulation",
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          "name": "Supply Current, internal reference off",
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          "name": "Supply Current, internal reference on",
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          "name": "Output Voltage Settling Time",
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          "name": "Digital-to-Analog Glitch Impulse",
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          "name": "Output Noise Spectral Density",
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          "conditions": "DAC code = midscale, 10 kHz; gain = 2, internal reference enable",
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        {
          "name": "SCLK Cycle Time",
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