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AD5684RBRUZ

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Analog Devices Digital To Analog Converters (DACs), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentdata convertersad5684rbruzfactory-2.0.0extractor-text

Verified AD5684RBRUZ

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 16 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AD5684RBRUZ · TSSOP-16 · 16 pins
  • ✓copper: 16 copper pads, none touching another net
  • ✓datasheet: all 16 pin names found in the 29-page datasheet
  • ✓distributor: lcsc C578274, digikey 505-AD5684RBRUZ-ND, mouser 584-AD5684RBRUZ
  • ✓family: TSSOP-16_4.4x5mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-r7a4gy0q/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 16 pins = 16 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 16 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ad5684rbruz.kicad_sym✓ ad5684rbruz.kicad_mod✓ ad5684rbruz.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs Publish 0.1.0 · Ray 2d ago
viewers ad5684rbruz: viewers · Ray 2d ago
ad5684rbruz-etched.glb Publish 0.1.0 · Ray 2d ago
ad5684rbruz-etched.step ad5684rbruz: factory component page (tier=mfr) · Ray 2d ago
ad5684rbruz-hero.glb ad5684rbruz: hero GLB from the etched model (keeps the MPN mark) · Ray 2d ago
ad5684rbruz-hero.overlay.json Publish 0.1.0 · Ray 2d ago
ad5684rbruz.glb Publish 0.1.0 · Ray 2d ago
ad5684rbruz.kicad_mod Publish 0.1.0 · Ray 2d ago
ad5684rbruz.kicad_sym Publish 0.1.0 · Ray 2d ago
ad5684rbruz.lbr Publish 0.1.0 · Ray 2d ago
ad5684rbruz.step Publish 0.1.0 · Ray 2d ago
package.json Publish 0.1.0 · Ray 2d ago
page.json Set visibility: public · Ray 2d ago
README.md Publish 0.1.0 · Ray 2d ago
verification.json Verified: Published by the parts factory: tier mfr, 16 pins · Ray 2d ago

AD5684RBRUZ

Analog Devices · Digital To Analog Converters (DACs) · TSSOP-16

AD5684RBRUZ from Analog Devices, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VREF power_in Common reference pin: reference output when using the internal reference (default) and reference input when using an external reference.
2 VOUTB output Analog output voltage from DAC B with rail-to-rail output amplifier.
3 VOUTA output Analog output voltage from DAC A with rail-to-rail output amplifier.
4 GND power_in Ground reference point for all circuitry on the part.
5 VDD power_in Power supply input, 2.7 V to 5.5 V, decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
6 VOUTC output Analog output voltage from DAC C with rail-to-rail output amplifier.
7 VOUTD output Analog output voltage from DAC D with rail-to-rail output amplifier.
8 SDO output Serial data output used to daisy-chain devices or for readback; data transferred on the rising edge of SCLK and valid on the falling edge.
9 LDAC input Load DAC input operated asynchronously or synchronously; pulsing low updates DAC registers simultaneously, and it can be tied permanently low.
10 GAIN input Span set pin: tied to GND gives 0 V to VREF output span, tied to VLOGIC gives 0 V to 2 × VREF for all four DACs.
11 VLOGIC power_in Digital power supply, 1.8 V to 5.5 V.
12 SCLK input Serial clock input; data is clocked into the shift register on the falling edge at up to 50 MHz.
13 SYNC input Active-low frame synchronization input; when low, data is transferred in on the falling edges of the next 24 clocks.
14 SDIN input Serial data input to the 24-bit input shift register, clocked on the falling edge of SCLK.
15 RESET input Asynchronous falling-edge-sensitive reset input; LDAC pulses are ignored while low and registers go to zero or midscale per RSTSEL.
16 RSTSEL input Power-on reset select: tied to GND powers up all DACs to zero scale, tied to VLOGIC powers up to midscale.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package TSSOP-16
Category Data Converters
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Resolution 12 Bits AD5684R 3
Relative Accuracy INL -1 0.12 1 LSB AD5684R, B grade 3
Differential Nonlinearity DNL -1 1 LSB Guaranteed monotonic by design 3
Zero-Code Error 0.4 1.5 mV All zeros loaded to DAC register 3
Offset Error -1.5 0.1 1.5 mV 3
Full-Scale Error -0.1 0.01 0.1 % of FSR All ones loaded to DAC register 3
Gain Error -0.1 0.02 0.1 % of FSR 3
Total Unadjusted Error (external reference) TUE -0.1 0.01 0.1 % of FSR External reference; gain = 2; TSSOP 3
Total Unadjusted Error (internal reference) TUE -0.2 0.2 % of FSR Internal reference; gain = 1; TSSOP 3
Offset Error Drift 1 µV/°C 3
Gain Temperature Coefficient 1 ppm Of FSR/°C 3
DC Power Supply Rejection Ratio PSRR 0.15 mV/V DAC code = midscale; VDD = 5 V ± 10% 3
DC Crosstalk, single channel full-scale change 2 µV Due to single channel, full-scale output change 3
DC Crosstalk, load current change 3 µV/mA Due to load current change 3
Capacitive Load Stability 2 nF RL = ∞ 3
Capacitive Load Stability 10 nF RL = 1 kΩ 3
Resistive Load 1 kΩ 3
Load Regulation 80 µV/mA 5 V ± 10%, DAC code = midscale; −30 mA ≤ IOUT ≤ 30 mA 3
Short-Circuit Current 40 mA VDD = 5 V 3
Load Impedance at Rails 25 Ω See Figure 33 3
Power-Up Time 2.5 µs Coming out of power-down mode; VDD = 5 V 3
Reference Output Voltage 2.4975 2.5025 V At ambient 3
Reference TC 2 5 ppm/°C See the Terminology section 3
Reference Output Impedance 0.04 Ω 4
Reference Output Voltage Noise 12 µV p-p 0.1 Hz to 10 Hz 4
Reference Output Voltage Noise Density 240 nV/√Hz At ambient; f = 10 kHz, CL = 10 nF 4
Reference Load Regulation Sourcing 20 µV/mA At ambient 4
Reference Load Regulation Sinking 40 µV/mA At ambient 4
Reference Output Current Load Capability -5 5 mA VDD ≥ 3 V 4
Reference Line Regulation 100 µV/V At ambient 4
Reference Thermal Hysteresis 125 ppm First cycle 4
Reference Thermal Hysteresis 25 ppm Additional cycles 4
Logic Input Current -2 2 µA Per pin 4
Logic Input Pin Capacitance 2 pF 4
Output Low Voltage (SDO) VOL 0.4 V ISINK = 200 μA 4
Floating State Output Capacitance (SDO) 4 pF 4
Logic Supply Voltage VLOGIC 1.62 5.5 V 4
Logic Supply Current ILOGIC 3 µA 4
Supply Voltage VDD 2.7 5.5 V Gain = 1 4
Supply Current, internal reference off IDD 0.59 0.7 mA Normal mode; internal reference off; VIH = VDD, VIL = GND 4
Supply Current, internal reference on IDD 1.1 1.3 mA Normal mode; internal reference on, at full scale 4
Supply Current, power-down IDD 1 4 µA All power-down modes; −40°C to +85°C 4
Supply Current, power-down IDD 6 µA All power-down modes; −40°C to +105°C 4
Output Voltage Settling Time 5 7 µs AD5684R; ¼ to ¾ scale settling to ±2 LSB 5
Slew Rate 0.8 V/µs 5
Digital-to-Analog Glitch Impulse 0.5 nV-sec 1 LSB change around major carry 5
Total Harmonic Distortion THD -80 dB At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz 5
Output Noise Spectral Density 300 nV/√Hz DAC code = midscale, 10 kHz; gain = 2, internal reference enable 5
SCLK Cycle Time t1 20 ns 2.7 V ≤ VLOGIC ≤ 5.5 V 5
Power-Up Time (exit power-down) 4.5 µs Exit power-down to normal mode, SYNC rising edge to 90% of DAC midscale value, output unloaded 6
VDD to GND VDD -0.3 7 V TA = 25°C 8
VLOGIC to GND VLOGIC -0.3 7 V TA = 25°C 8
Operating Temperature Range -40 105 °C 8
Storage Temperature Range -65 150 °C 8
Junction Temperature TJ 125 °C 8
Reflow Soldering Peak Temperature, Pb Free 260 °C J-STD-020 8
16-Lead TSSOP Thermal Impedance θJA 112.6 °C/W 0 Airflow, 4-Layer Board 8

CAD (KiCad official)

  • Symbol: AD5684RBRUZ
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: ad5684rbruz-etched.step / ad5684rbruz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5684rbruz.step / ad5684rbruz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (29 pp, sha256 16c7cb655e87649e, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF