AD5676RBRUZ-REEL7

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  "slug": "ad5676rbruz-reel7",
  "title": "AD5676RBRUZ-REEL7",
  "brief": "Analog Devices Digital To Analog Converters (DAC), TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
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    "data acquisition",
    "ad5676rbruz-reel7",
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    "mpn": "AD5676RBRUZ-REEL7",
    "manufacturer": "Analog Devices",
    "package": "TSSOP-20",
    "pin_count": 20,
    "category": "Data Acquisition",
    "subcategory": "Digital To Analog Converters (DAC)",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588886773615235072",
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    "distributor_links": {
      "lcsc": "C515876",
      "digikey": "505-AD5676RBRUZ-REEL7TR-ND",
      "mouser": "584-AD5676RBRUZREEL7"
    },
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    "pins": [
      {
        "number": "1",
        "name": "VOUT1",
        "type": "output",
        "description": "Analog output voltage from DAC 1; the output amplifier has rail-to-rail operation."
      },
      {
        "number": "2",
        "name": "VOUT0",
        "type": "output",
        "description": "Analog output voltage from DAC 0; the output amplifier has rail-to-rail operation."
      },
      {
        "number": "3",
        "name": "VDD",
        "type": "power_in",
        "description": "Power supply input; the devices operate from 2.7 V to 5.5 V and should be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND."
      },
      {
        "number": "4",
        "name": "VLOGIC",
        "type": "power_in",
        "description": "Digital power supply; the voltage on this pin ranges from 1.62 V to 5.5 V."
      },
      {
        "number": "5",
        "name": "SYNC",
        "type": "input",
        "description": "Active-low frame synchronization input; when SYNC goes low, data transfers in on the falling edges of the next 24 clocks."
      },
      {
        "number": "6",
        "name": "SCLK",
        "type": "input",
        "description": "Serial clock input; data is clocked into the input shift register on the falling edge, at rates of up to 50 MHz."
      },
      {
        "number": "7",
        "name": "SDI",
        "type": "input",
        "description": "Serial data input to a 24-bit input shift register; data is clocked into the register on the falling edge of the serial clock."
      },
      {
        "number": "8",
        "name": "GAIN",
        "type": "input",
        "description": "Span set pin; tying it to GND sets all eight DAC outputs to a span of 0 V to VREF, and tying it to VLOGIC sets a span of 0 V to 2 × VREF."
      },
      {
        "number": "9",
        "name": "VOUT7",
        "type": "output",
        "description": "Analog output voltage from DAC 7; the output amplifier has rail-to-rail operation."
      },
      {
        "number": "10",
        "name": "VOUT6",
        "type": "output",
        "description": "Analog output voltage from DAC 6; the output amplifier has rail-to-rail operation."
      },
      {
        "number": "11",
        "name": "VOUT5",
        "type": "output",
        "description": "Analog output voltage from DAC 5; the output amplifier has rail-to-rail operation."
      },
      {
        "number": "12",
        "name": "VOUT4",
        "type": "output",
        "description": "Analog output voltage from DAC 4; the output amplifier has rail-to-rail operation."
      },
      {
        "number": "13",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference point for all circuitry on the device."
      },
      {
        "number": "14",
        "name": "RSTSEL",
        "type": "input",
        "description": "Power-on reset pin; tying it to GND powers up all eight DACs to zero scale, and tying it to VLOGIC powers up all eight DACs to midscale."
      },
      {
        "number": "15",
        "name": "LDAC",
        "type": "input",
        "description": "Load DAC input; pulsing it low updates any or all DAC registers from their input registers so all outputs update simultaneously, and it may be tied permanently low."
      },
      {
        "number": "16",
        "name": "SDO",
        "type": "output",
        "description": "Serial data output used for daisy-chaining or readback; data transfers on the rising edge of SCLK and is valid on the falling edge."
      },
      {
        "number": "17",
        "name": "RESET",
        "type": "input",
        "description": "Asynchronous reset input that is falling-edge sensitive; while RESET is low, LDAC pulses are ignored, and activation loads zero scale or midscale per the RSTSEL pin."
      },
      {
        "number": "18",
        "name": "VREFOUT",
        "type": "output",
        "description": "Reference output voltage; this is the reference output pin when the internal reference is used."
      },
      {
        "number": "19",
        "name": "VOUT3",
        "type": "output",
        "description": "Analog output voltage from DAC 3; the output amplifier has rail-to-rail operation."
      },
      {
        "number": "20",
        "name": "VOUT2",
        "type": "output",
        "description": "Analog output voltage from DAC 2; the output amplifier has rail-to-rail operation."
      }
    ],
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        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The TSSOP pin configuration figure (Figure 6) text is out of order in the extraction, so pin positio; GAIN (pin 8) and RSTSEL (pin 14) are listed as N/A on the LFCSP package but are present on the TSSOP; The datasheet covers the AD5672R/AD5676R family. The ordering guide lists AD5676RBRUZ-REEL7 as a 16-"
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        "at": "2026-10-21T00:48:11"
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  "metadata": {
    "specs": {
      "Manufacturer": "Analog Devices",
      "Package": "TSSOP-20",
      "Category": "Data Acquisition",
      "Pins": "20"
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          "name": "DC Power Supply Rejection Ratio (PSRR)",
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