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AD5676RBRUZ-REEL7

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Analog Devices Digital To Analog Converters (DAC), TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AD5676RBRUZ-REEL7

Analog Devices · Digital To Analog Converters (DAC) · TSSOP-20

AD5676RBRUZ-REEL7 from Analog Devices, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VOUT1 output Analog output voltage from DAC 1; the output amplifier has rail-to-rail operation.
2 VOUT0 output Analog output voltage from DAC 0; the output amplifier has rail-to-rail operation.
3 VDD power_in Power supply input; the devices operate from 2.7 V to 5.5 V and should be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
4 VLOGIC power_in Digital power supply; the voltage on this pin ranges from 1.62 V to 5.5 V.
5 SYNC input Active-low frame synchronization input; when SYNC goes low, data transfers in on the falling edges of the next 24 clocks.
6 SCLK input Serial clock input; data is clocked into the input shift register on the falling edge, at rates of up to 50 MHz.
7 SDI input Serial data input to a 24-bit input shift register; data is clocked into the register on the falling edge of the serial clock.
8 GAIN input Span set pin; tying it to GND sets all eight DAC outputs to a span of 0 V to VREF, and tying it to VLOGIC sets a span of 0 V to 2 × VREF.
9 VOUT7 output Analog output voltage from DAC 7; the output amplifier has rail-to-rail operation.
10 VOUT6 output Analog output voltage from DAC 6; the output amplifier has rail-to-rail operation.
11 VOUT5 output Analog output voltage from DAC 5; the output amplifier has rail-to-rail operation.
12 VOUT4 output Analog output voltage from DAC 4; the output amplifier has rail-to-rail operation.
13 GND power_in Ground reference point for all circuitry on the device.
14 RSTSEL input Power-on reset pin; tying it to GND powers up all eight DACs to zero scale, and tying it to VLOGIC powers up all eight DACs to midscale.
15 LDAC input Load DAC input; pulsing it low updates any or all DAC registers from their input registers so all outputs update simultaneously, and it may be tied permanently low.
16 SDO output Serial data output used for daisy-chaining or readback; data transfers on the rising edge of SCLK and is valid on the falling edge.
17 RESET input Asynchronous reset input that is falling-edge sensitive; while RESET is low, LDAC pulses are ignored, and activation loads zero scale or midscale per the RSTSEL pin.
18 VREFOUT output Reference output voltage; this is the reference output pin when the internal reference is used.
19 VOUT3 output Analog output voltage from DAC 3; the output amplifier has rail-to-rail operation.
20 VOUT2 output Analog output voltage from DAC 2; the output amplifier has rail-to-rail operation.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package TSSOP-20
Category Data Acquisition
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Relative Accuracy (INL), Gain = 1 INL -3 1.8 3 LSB Gain = 1 6
Relative Accuracy (INL), Gain = 2 INL -3 1.7 3 LSB Gain = 2 6
Differential Nonlinearity (DNL), Gain = 1 DNL -1 0.7 1 LSB Gain = 1 6
Differential Nonlinearity (DNL), Gain = 2 DNL -1 0.5 1 LSB Gain = 2 6
Zero Code Error 0.8 1.6 mV Gain = 1 or gain = 2 6
Offset Error, Gain = 1 -2 -0.75 2 mV Gain = 1 6
Offset Error, Gain = 2 -1.5 -0.1 1.5 mV Gain = 2 6
Full-Scale Error, Gain = 1 -0.14 -0.018 0.14 % of FSR Gain = 1 6
Full-Scale Error, Gain = 2 -0.07 -0.013 0.07 % of FSR Gain = 2 6
Gain Error, Gain = 1 -0.12 0.04 0.12 % of FSR Gain = 1 6
Gain Error, Gain = 2 -0.06 -0.02 0.06 % of FSR Gain = 2 6
Total Unadjusted Error (TUE), Gain = 1 TUE -0.18 0.03 0.18 % of FSR Gain = 1 6
Total Unadjusted Error (TUE), Gain = 2 TUE -0.14 0.006 0.14 % of FSR Gain = 2 6
Offset Error Drift -1 1 µV/°C 6
DC Power Supply Rejection Ratio (PSRR) PSRR 0.25 mV/V DAC code = midscale, VDD = 5 V ± 10% 6
Output Voltage Range, Gain = 1 VOUT 0 2.5 V Gain = 1 6
Output Voltage Range, Gain = 2 VOUT 0 5 V Gain = 2 6
Output Current Drive IOUT 15 mA 6
Capacitive Load Stability CL 2 nF RL = ∞ 6
Capacitive Load Stability CL 10 nF RL = 1 kΩ 6
Reference Output Voltage VREFOUT 2.4975 2.5025 V 6
Reference Temperature Coefficient (B grade) 2 5 ppm/°C See the Terminology section (box method) 6
Logic Input Current IIN -1 1 µA Per pin 7
Logic Output Low Voltage (SDO) VOL 0.4 V ISINK = 200 µA 7
VLOGIC Supply Voltage VLOGIC 1.62 5.5 V 7
VDD Supply Voltage, Gain = 1 VDD 2.7 5.5 V Gain = 1 7
VDD Supply Voltage, Gain = 2 VDD 5.5 V Gain = 2 (minimum printed as VREF+ 1.5 V) 7
VLOGIC Supply Current, Power-On, −40°C to +105°C ILOGIC 1 µA Power-on, −40°C to +105°C 7
VLOGIC Supply Current, Power-On, −40°C to +125°C ILOGIC 1.3 µA Power-on, −40°C to +125°C 7
VLOGIC Supply Current, Power-Down, −40°C to +105°C ILOGIC 0.5 µA Power-down, −40°C to +105°C 7
VLOGIC Supply Current, Power-Down, −40°C to +125°C ILOGIC 1.3 µA Power-down, −40°C to +125°C 7
VDD Supply Current, Normal Mode, Internal Reference Off, −40°C to +85°C IDD 1.1 1.26 mA Internal reference off, −40°C to +85°C 7
VDD Supply Current, Normal Mode, Internal Reference On, −40°C to +85°C IDD 1.8 2 mA Internal reference on, −40°C to +85°C 7
VDD Supply Current, Normal Mode, Internal Reference Off IDD 1.1 1.3 mA Internal reference off 7
VDD Supply Current, Normal Mode, Internal Reference On IDD 1.8 2.1 mA Internal reference on 7
All Power-Down Modes, Tristate to 1 kΩ, −40°C to +85°C IDD 1 1.7 µA Tristate to 1 kΩ, −40°C to +85°C 7
All Power-Down Modes, Power-down to 1 kΩ, −40°C to +85°C IDD 1 1.7 µA Power-down to 1 kΩ, −40°C to +85°C 7
All Power-Down Modes, Tristate, −40°C to +105°C IDD 1 2.5 µA Tristate, −40°C to +105°C 7
All Power-Down Modes, Power-down to 1 kΩ, −40°C to +105°C IDD 1 2.5 µA Power-down to 1 kΩ, −40°C to +105°C 7
All Power-Down Modes, Tristate to 1 kΩ, −40°C to +125°C IDD 1 5.5 µA Tristate to 1 kΩ, −40°C to +125°C 7
All Power-Down Modes, Power-down to 1 kΩ, −40°C to +125°C IDD 1 5.5 µA Power-down to 1 kΩ, −40°C to +125°C 7
Output Voltage Settling Time, ¼ to ¾ Scale tS 5 8 µs ¼ to ¾ scale settling to ±2 LSB 8
Absolute Maximum: VDD to GND VDD -0.3 7 V 12
Absolute Maximum: VLOGIC to GND VLOGIC -0.3 7 V 12
Absolute Maximum: VOUTx to GND VOUTx -0.3 V Upper limit printed as VDD + 0.3 V 12
Absolute Maximum: VREF to GND VREF -0.3 V Upper limit printed as VDD + 0.3 V 12
Absolute Maximum: Digital Input Voltage to GND -0.3 V Upper limit printed as VLOGIC + 0.3 V 12
Absolute Maximum: Operating Temperature Range TA -40 125 °C 12
Absolute Maximum: Storage Temperature Range TSTG -65 150 °C 12
Absolute Maximum: Junction Temperature TJ 125 °C 12
Absolute Maximum: Reflow Soldering Peak Temperature, Pb-Free 260 °C J-STD-020 12
Recommended Operating: VDD VDD 2.7 5.5 V Gain = 1 4
Recommended Operating: VLOGIC VLOGIC 1.62 5.5 V 4
Recommended Operating: Ambient Temperature Range TA -40 125 °C Specifications TMIN to TMAX 4
Thermal Resistance, Junction-to-Ambient (TSSOP RU-20) θJA 98.65 °C/W JEDEC 2S2P thermal test board 12
Thermal Resistance, Junction-to-Board (TSSOP RU-20) θJB 44.39 °C/W 12
Thermal Resistance, Junction-to-Case (TSSOP RU-20) θJC 17.58 °C/W 12
Thermal Characterization, Junction-to-Top (TSSOP RU-20) ΨJT 1.77 °C/W 12
Thermal Characterization, Junction-to-Board (TSSOP RU-20) ΨJB 43.9 °C/W 12

CAD (KiCad official)

  • Symbol: AD5676RBRUZ-REEL7
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: ad5676rbruz-reel7-etched.step / ad5676rbruz-reel7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5676rbruz-reel7.step / ad5676rbruz-reel7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (35 pp, sha256 8a157520f655cbaa, retrieved 2026-10-21, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF