AD5541ABRMZ-REEL7

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  "title": "AD5541ABRMZ-REEL7",
  "brief": "Analog Devices Digital To Analog Converters (DAC), MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
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    "mpn": "AD5541ABRMZ-REEL7",
    "manufacturer": "Analog Devices",
    "package": "MSOP-10",
    "pin_count": 10,
    "category": "Data Acquisition",
    "subcategory": "Digital To Analog Converters (DAC)",
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      "digikey": "505-AD5541ABRMZ-REEL7TR-ND",
      "mouser": "584-AD5541ABRMZ-R7"
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      {
        "number": "1",
        "name": "VDD",
        "type": "power_in",
        "description": "Analog supply voltage, specified from 2.7 V to 5.5 V with all digital inputs at 0 V, VLOGIC, or VDD."
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      {
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        "description": "Unbuffered analog DAC output, swinging from 0 V to VREF − 1 LSB in unipolar operation and capable of driving unbuffered loads of 60 kΩ."
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      {
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        "name": "REF",
        "type": "input",
        "description": "Voltage reference input for the DAC, to be connected to an external 2.5 V reference that can range from 2 V to VDD."
      },
      {
        "number": "5",
        "name": "CS",
        "type": "input",
        "description": "Chip select logic input that frames the serial data input; data can be loaded to the part only while CS is low."
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        "number": "6",
        "name": "SCLK",
        "type": "input",
        "description": "Serial clock input; data is clocked into the serial input register on the rising edge of SCLK, with a duty cycle between 40% and 60%."
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        "number": "7",
        "name": "DIN",
        "type": "input",
        "description": "Serial data input accepting 16-bit words, clocked into the serial input register on the rising edge of SCLK."
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      {
        "number": "8",
        "name": "LDAC",
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        "description": "When taken low, the DAC register is simultaneously updated with the contents of the serial input register."
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      {
        "number": "9",
        "name": "DGND",
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      {
        "number": "10",
        "name": "VLOGIC",
        "type": "power_in",
        "description": "Logic power supply, specified from 1.8 V to 5.5 V."
      }
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      "Manufacturer": "Analog Devices",
      "Package": "MSOP-10",
      "Category": "Data Acquisition",
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          "name": "SCLK cycle frequency",
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        {
          "name": "SCLK cycle time",
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          "typ": null,
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        {
          "name": "SCLK cycle time",
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          "typ": null,
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          "name": "SCLK high time",
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        {
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          "name": "CS low to SCLK high setup",
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        {
          "name": "SCLK high to CS high hold time",
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          "typ": null,
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          "conditions": "Limit at 2.7 V ≤ VLOGIC ≤ 5.5 V; VDD = 5 V",
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        {
          "name": "Data setup time",
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          "typ": null,
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          "conditions": "Limit at 1.8 V ≤ VLOGIC ≤ 2.7 V; VDD = 5 V",
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          "name": "Data setup time",
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          "conditions": "Limit at 2.7 V ≤ VLOGIC ≤ 5.5 V; VDD = 5 V",
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        {
          "name": "Data hold time",
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          "conditions": "VINH = 90% of VDD, VINL = 10% of VDD; Limit at 1.8 V ≤ VLOGIC ≤ 2.7 V",
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        {
          "name": "Data hold time",
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          "name": "LDAC pulse width",
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          "conditions": "Limit at 1.8 V ≤ VLOGIC ≤ 2.7 V; VDD = 5 V",
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        {
          "name": "CS high to LDAC low setup",
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        {
          "name": "CS high time between active periods",
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          "conditions": "Limit at 1.8 V ≤ VLOGIC ≤ 2.7 V; VDD = 5 V",
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          "name": "VDD to AGND",
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        {
          "name": "VLOGIC to DGND",
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        {
          "name": "Digital Input Voltage to DGND",
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          "min": -0.3,
          "typ": null,
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