component
AD5541ABRMZ-REEL7
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Analog Devices Digital To Analog Converters (DAC), MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownAD5541ABRMZ-REEL7
Analog Devices · Digital To Analog Converters (DAC) · MSOP-10
AD5541ABRMZ-REEL7 from Analog Devices, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Analog supply voltage, specified from 2.7 V to 5.5 V with all digital inputs at 0 V, VLOGIC, or VDD. |
| 2 | VOUT | output | Unbuffered analog DAC output, swinging from 0 V to VREF − 1 LSB in unipolar operation and capable of driving unbuffered loads of 60 kΩ. |
| 3 | AGND | power_in | Ground reference point for the analog circuitry. |
| 4 | REF | input | Voltage reference input for the DAC, to be connected to an external 2.5 V reference that can range from 2 V to VDD. |
| 5 | CS | input | Chip select logic input that frames the serial data input; data can be loaded to the part only while CS is low. |
| 6 | SCLK | input | Serial clock input; data is clocked into the serial input register on the rising edge of SCLK, with a duty cycle between 40% and 60%. |
| 7 | DIN | input | Serial data input accepting 16-bit words, clocked into the serial input register on the rising edge of SCLK. |
| 8 | LDAC | input | When taken low, the DAC register is simultaneously updated with the contents of the serial input register. |
| 9 | DGND | power_in | Ground reference for the digital circuitry. |
| 10 | VLOGIC | power_in | Logic power supply, specified from 1.8 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | MSOP-10 |
| Category | Data Acquisition |
| Pins | 10 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Relative Accuracy (INL) | INL | -1 | 0.5 | 1 | LSB | B grade | 3 |
| Differential Nonlinearity (DNL) | DNL | -1 | 0.5 | 1 | LSB | Guaranteed monotonic | 3 |
| Gain Error | -2 | 0.5 | 2 | LSB | TA = 25°C | 3 | |
| Gain Error | -3 | 3 | LSB | −40°C < TA < +85°C | 3 | ||
| Gain Error | -4 | 4 | LSB | −40°C < TA < +125°C | 3 | ||
| Gain Error Temperature Coefficient | -0.1 | 0.1 | ppm/°C | 3 | |||
| Zero-Code Error | -0.7 | 0.3 | 0.7 | LSB | TA = 25°C | 3 | |
| Zero-Code Error | -1.5 | 1.5 | LSB | −40°C < TA < +85°C | 3 | ||
| Zero-Code Error | -3 | 3 | LSB | −40°C < TA < +125°C | 3 | ||
| Zero-Code Temperature Coefficient | -0.05 | 0.05 | ppm/°C | 3 | |||
| DC Power Supply Rejection Ratio | -1 | 1 | LSB | ΔVDD ± 10% | 3 | ||
| Output Voltage Range | 0 | V | Unipolar operation; printed max is VREF − 1 LSB | 3 | |||
| Reference Input Range | 2 | V | Printed max is VDD | 3 | |||
| Input Current | -1 | 1 | µA | 3 | |||
| Input Low Voltage | VINL | 0.4 | V | VLOGIC = 1.8 V to 5.5 V | 3 | ||
| Input Low Voltage | VINL | 0.8 | V | VLOGIC = 2.7 V to 5.5 V | 3 | ||
| Input High Voltage | VINH | 2.4 | V | VLOGIC = 4.5 V to 5.5 V | 3 | ||
| Input High Voltage | VINH | 1.8 | V | VLOGIC = 2.7 V to 3.6 V | 3 | ||
| Input High Voltage | VINH | 1.3 | V | VLOGIC = 1.8 V to 2.7 V | 3 | ||
| VDD Supply Voltage | VDD | 2.7 | 5.5 | V | All digital inputs at 0 V, VLOGIC, or VDD | 3 | |
| Supply Current (IDD) | IDD | 125 | 150 | µA | VIH = VLOGIC or VDD and VIL = GND | 3 | |
| Logic Supply Voltage | VLOGIC | 1.8 | 5.5 | V | 3 | ||
| Logic Supply Current (ILOGIC) | ILOGIC | 15 | 24 | µA | All digital inputs at 0 V, VLOGIC, or VDD | 3 | |
| Power Dissipation | 0.625 | 0.825 | mW | 3 | |||
| SCLK cycle frequency | fSCLK | 14 | MHz | Limit at 1.8 V ≤ VLOGIC ≤ 2.7 V; VDD = 5 V | 5 | ||
| SCLK cycle frequency | fSCLK | 50 | MHz | Limit at 2.7 V ≤ VLOGIC ≤ 5.5 V; VDD = 5 V | 5 | ||
| SCLK cycle time | t1 | 70 | ns | Limit at 1.8 V ≤ VLOGIC ≤ 2.7 V; VDD = 5 V | 5 | ||
| SCLK cycle time | t1 | 20 | ns | Limit at 2.7 V ≤ VLOGIC ≤ 5.5 V; VDD = 5 V | 5 | ||
| SCLK high time | t2 | 35 | ns | Limit at 1.8 V ≤ VLOGIC ≤ 2.7 V; VDD = 5 V | 5 | ||
| SCLK high time | t2 | 10 | ns | Limit at 2.7 V ≤ VLOGIC ≤ 5.5 V; VDD = 5 V | 5 | ||
| SCLK low time | t3 | 35 | ns | Limit at 1.8 V ≤ VLOGIC ≤ 2.7 V; VDD = 5 V | 5 | ||
| SCLK low time | t3 | 10 | ns | Limit at 2.7 V ≤ VLOGIC ≤ 5.5 V; VDD = 5 V | 5 | ||
| CS low to SCLK high setup | t4 | 5 | ns | Limit at 1.8 V ≤ VLOGIC ≤ 2.7 V; VDD = 5 V | 5 | ||
| CS high to SCLK high setup | t5 | 5 | ns | Limit at 1.8 V ≤ VLOGIC ≤ 2.7 V; VDD = 5 V | 5 | ||
| SCLK high to CS low hold time | t6 | 5 | ns | Limit at 1.8 V ≤ VLOGIC ≤ 2.7 V; VDD = 5 V | 5 | ||
| SCLK high to CS high hold time | t7 | 10 | ns | Limit at 1.8 V ≤ VLOGIC ≤ 2.7 V; VDD = 5 V | 5 | ||
| SCLK high to CS high hold time | t7 | 5 | ns | Limit at 2.7 V ≤ VLOGIC ≤ 5.5 V; VDD = 5 V | 5 | ||
| Data setup time | t8 | 35 | ns | Limit at 1.8 V ≤ VLOGIC ≤ 2.7 V; VDD = 5 V | 5 | ||
| Data setup time | t8 | 10 | ns | Limit at 2.7 V ≤ VLOGIC ≤ 5.5 V; VDD = 5 V | 5 | ||
| Data hold time | t9 | 5 | ns | VINH = 90% of VDD, VINL = 10% of VDD; Limit at 1.8 V ≤ VLOGIC ≤ 2.7 V | 5 | ||
| Data hold time | t9 | 4 | ns | VINH = 90% of VDD, VINL = 10% of VDD; Limit at 2.7 V ≤ VLOGIC ≤ 5.5 V | 5 | ||
| LDAC pulse width | t10 | 20 | ns | Limit at 1.8 V ≤ VLOGIC ≤ 2.7 V; VDD = 5 V | 5 | ||
| CS high to LDAC low setup | t11 | 10 | ns | Limit at 1.8 V ≤ VLOGIC ≤ 2.7 V; VDD = 5 V | 5 | ||
| CS high time between active periods | t12 | 15 | ns | Limit at 1.8 V ≤ VLOGIC ≤ 2.7 V; VDD = 5 V | 5 | ||
| VDD to AGND | VDD | -0.3 | 6 | V | 6 | ||
| VLOGIC to DGND | VLOGIC | -0.3 | 6 | V | 6 | ||
| Digital Input Voltage to DGND | -0.3 | V | Printed max is VDD/VLOGIC + 0.3 V | 6 | |||
| VOUT to AGND | VOUT | -0.3 | V | Printed max is VDD + 0.3 V | 6 | ||
| AGND to DGND | -0.3 | 0.3 | V | 6 | |||
| Input Current to Any Pin Except Supplies | -10 | 10 | mA | 6 | |||
| Operating Temperature Range (Industrial, B Version) | -40 | 125 | °C | Industrial (A, B Versions) | 6 | ||
| Thermal Impedance, junction-to-ambient (θJA) | θJA | 135 | °C/W | MSOP (RM-10) | 6 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | Abs | 2 Human body model (HBM) classification. Stresses at or above those listed under Absolute Maximum | 6 |
CAD (KiCad official)
- Symbol:
AD5541ABRMZ-REEL7 - Footprint:
Package_SO:MSOP-10_3x3mm_P0.5mm - 3D model: MSOP-10 (KiCad packages3D, STEP)
- 3D model files:
ad5541abrmz-reel7-etched.step/ad5541abrmz-reel7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad5541abrmz-reel7.step/ad5541abrmz-reel7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (20 pp, sha256
aec921fa32a27ede, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).