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Ray Set visibility: public 47a07ca 2d ago
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{
  "schema_version": 1,
  "type": "component",
  "slug": "ad5429yruz",
  "title": "AD5429YRUZ",
  "brief": "Analog Devices Digital To Analog Converters (DACs), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
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    "adc-dac-data conversion",
    "ad5429yruz",
    "factory-2.0.0",
    "extractor-text"
  ],
  "component": {
    "mpn": "AD5429YRUZ",
    "manufacturer": "Analog Devices",
    "package": "TSSOP-16",
    "pin_count": 16,
    "category": "ADC/DAC/Data Conversion",
    "subcategory": "Digital To Analog Converters (DACs)",
    "datasheet": "https://www.analog.com/media/en/technical-documentation/data-sheets/AD5429_5439_5449.pdf",
    "parts": {
      "symbol": "ad5429yruz.kicad_sym",
      "footprint": "ad5429yruz.kicad_mod",
      "model_3d": "ad5429yruz-hero.glb",
      "model_3d_plain": "ad5429yruz-etched.glb",
      "model_3d_step": "ad5429yruz-etched.step",
      "model_3d_step_plain": "ad5429yruz.step",
      "lbr": "ad5429yruz.lbr"
    },
    "distributor_links": {
      "lcsc": "C649743",
      "digikey": "AD5429YRUZ-ND",
      "mouser": "584-AD5429YRUZ"
    },
    "distributor_check": {
      "checked_at": "2026-10-31T18:39:23Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "AD5429YRUZ-ND",
        "status": "found"
      },
      "mouser": {
        "pn": "584-AD5429YRUZ",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "IOUT1A",
        "type": "output",
        "description": "DAC A current output."
      },
      {
        "number": "2",
        "name": "IOUT2A",
        "type": "passive",
        "description": "DAC A analog ground, typically tied to system analog ground but can be biased to achieve single-supply operation."
      },
      {
        "number": "3",
        "name": "RFBA",
        "type": "passive",
        "description": "DAC A feedback resistor pin that establishes voltage output by connecting to an external amplifier output."
      },
      {
        "number": "4",
        "name": "VREFA",
        "type": "input",
        "description": "DAC A reference voltage input pin (reference input range ±10 V)."
      },
      {
        "number": "5",
        "name": "GND",
        "type": "power_in",
        "description": "Ground pin."
      },
      {
        "number": "6",
        "name": "LDAC",
        "type": "input",
        "description": "Load DAC input allowing asynchronous update when low, or automatic synchronous update if held permanently low (on the 16th clock falling edge in standalone mode, or SYNC rising edge in daisy-chain mode)."
      },
      {
        "number": "7",
        "name": "SCLK",
        "type": "input",
        "description": "Serial clock input; data is clocked into the shift register on the falling edge by default, or on the rising edge via control bits."
      },
      {
        "number": "8",
        "name": "SDIN",
        "type": "input",
        "description": "Serial data input; data is clocked into the 16-bit input register on the active edge of SCLK (falling edge by default)."
      },
      {
        "number": "9",
        "name": "SDO",
        "type": "output",
        "description": "Serial data output for daisy-chaining and DAC register readback, clocked out on the edge opposite to the one loading the shift register."
      },
      {
        "number": "10",
        "name": "SYNC",
        "type": "input",
        "description": "Active-low frame synchronization input; when low it powers on the SCLK and DIN buffers and enables the input shift register, with data latched on the 16th active clock edge in standalone mode."
      },
      {
        "number": "11",
        "name": "CLR",
        "type": "input",
        "description": "Active-low control input that clears the DAC output, input, and DAC registers, to zero scale or midscale as configured."
      },
      {
        "number": "12",
        "name": "VDD",
        "type": "power_in",
        "description": "Positive power supply input, operating from 2.5 V to 5.5 V."
      },
      {
        "number": "13",
        "name": "VREFB",
        "type": "input",
        "description": "DAC B reference voltage input pin (reference input range ±10 V)."
      },
      {
        "number": "14",
        "name": "RFBB",
        "type": "passive",
        "description": "DAC B feedback resistor pin that establishes voltage output by connecting to an external amplifier output."
      },
      {
        "number": "15",
        "name": "IOUT2B",
        "type": "passive",
        "description": "DAC B analog ground, typically tied to system analog ground but can be biased to achieve single-supply operation."
      },
      {
        "number": "16",
        "name": "IOUT1B",
        "type": "output",
        "description": "DAC B current output."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-sonnet-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Pin types for current outputs (IOUT1x), analog-ground-like IOUT2x and feedback RFBx were assigned by"
        ],
        "pages_sent": 7,
        "cost_usd": 0.0944,
        "at": "2026-10-31T18:39:10"
      },
      "datasheet": {
        "url": "https://www.analog.com/media/en/technical-documentation/data-sheets/AD5429_5439_5449.pdf",
        "pages": 28,
        "sha256": "92e73915f7ff8583",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
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    "models_3d": [
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        "file": "ad5429yruz.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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          5,
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        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "6ad5e98224d02a427d9a6b929a28dbc158b9925fba5adec12db05079f1016948",
        "checked": "2026-10-31",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "ad5429yruz-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "66954da9d46732fb758c90a6bd31092ff6964369db08b99818354a7b0e4c945a",
        "checked": "2026-10-31",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ],
    "package_dims": {
      "package_code": "RU-16",
      "source_page": 26,
      "D": {
        "nom_mm": 5,
        "range_mm": [
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          5.1
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      },
      "E1": {
        "nom_mm": 4.4,
        "range_mm": [
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      },
      "E": {
        "nom_mm": 6.4,
        "range_mm": [
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      "e": {
        "nom_mm": 0.65,
        "range_mm": [
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      },
      "A": {
        "nom_mm": 1.2,
        "range_mm": [
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      },
      "source": "datasheet package drawing, every number found on its page (extract_pins --task dims)",
      "model_check": {
        "file": "ad5429yruz.step",
        "verdict": "PASS",
        "reasons": [
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        "by": "factory/package_fit.py"
      }
    }
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Analog Devices",
      "Package": "TSSOP-16",
      "Category": "ADC/DAC/Data Conversion",
      "Pins": "16"
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    "characteristics": {
      "version": 1,
      "source": "datasheet",
      "datasheet_sha256": "92e73915f7ff8583aa185a4db5cf857c8666e8a76a2c895f821b269f2844226b",
      "rows": [
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          "name": "Relative Accuracy",
          "symbol": "INL",
          "kind": "electrical",
          "unit": "LSB",
          "min": -0.5,
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          "max": 0.5,
          "conditions": "AD5429",
          "source_page": 3,
          "source": "datasheet"
        },
        {
          "name": "Differential Nonlinearity",
          "symbol": "DNL",
          "kind": "electrical",
          "unit": "LSB",
          "min": -1,
          "typ": null,
          "max": 1,
          "conditions": "Guaranteed monotonic, AD5429",
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          "name": "Output Leakage Current",
          "symbol": "",
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          "min": -5,
          "typ": null,
          "max": 5,
          "conditions": "Data = 0x0000, TA = 25°C, IOUT1",
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          "name": "Output Leakage Current",
          "symbol": "",
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          "conditions": "Data = 0x0000, IOUT1",
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        {
          "name": "VREFA, VREFB Input Resistance",
          "symbol": "",
          "kind": "electrical",
          "unit": "kΩ",
          "min": 9,
          "typ": 11,
          "max": 13,
          "conditions": "Input resistance temperature coefficient = −50 ppm/°C",
          "source_page": 3,
          "source": "datasheet"
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        {
          "name": "VREFA-to-VREFB Input Resistance Mismatch",
          "symbol": "",
          "kind": "electrical",
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          "conditions": "Typical = 25°C, maximum = 125°C",
          "source_page": 3,
          "source": "datasheet"
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        {
          "name": "Input Voltage High",
          "symbol": "VIH",
          "kind": "electrical",
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          "min": 1.7,
          "typ": null,
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          "conditions": "VDD = 3.6 V to 5.5 V",
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          "name": "Input Voltage Low",
          "symbol": "VIL",
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          "min": null,
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          "name": "Input Voltage Low",
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          "conditions": "VDD = 2.5 V to 2.7 V",
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          "source": "datasheet"
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          "name": "Output Low Voltage",
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          "max": 0.4,
          "conditions": "VDD = 4.5 V to 5.5 V, ISINK = 200 µA",
          "source_page": 3,
          "source": "datasheet"
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        {
          "name": "Input Leakage Current",
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        {
          "name": "Digital Input Capacitance",
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          "source": "datasheet"
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        {
          "name": "Output Voltage Settling Time",
          "symbol": "",
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          "unit": "ns",
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          "max": 120,
          "conditions": "Measured to ±1 mV of FS",
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        {
          "name": "Output Voltage Settling Time",
          "symbol": "",
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          "conditions": "Measured to ±4 mV of FS",
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        {
          "name": "Output Voltage Settling Time",
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          "min": null,
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          "conditions": "Measured to ±16 mV of FS",
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        {
          "name": "Digital Delay",
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          "name": "Output Capacitance",
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          "max": 17,
          "conditions": "DAC latches loaded with all 0s",
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          "name": "Output Capacitance",
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          "conditions": "DAC latches loaded with all 1s",
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        {
          "name": "Power Supply Range",
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          "source_page": 4,
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        {
          "name": "Supply Current",
          "symbol": "IDD",
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          "unit": "µA",
          "min": null,
          "typ": 0.5,
          "max": 10,
          "conditions": "TA = −40°C to +125°C, logic inputs = 0 V or VDD",
          "source_page": 4,
          "source": "datasheet"
        },
        {
          "name": "Supply Current",
          "symbol": "IDD",
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          "unit": "µA",
          "min": null,
          "typ": 0.7,
          "max": null,
          "conditions": "TA = 25°C, logic inputs = 0 V or VDD",
          "source_page": 4,
          "source": "datasheet"
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        {
          "name": "Maximum clock frequency",
          "symbol": "fSCLK",
          "kind": "timing",
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          "min": null,
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        {
          "name": "SCLK cycle time",
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        {
          "name": "SCLK high time",
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        {
          "name": "SCLK low time",
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          "source_page": 5,
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        {
          "name": "SYNC falling edge to SCLK falling edge setup time",
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        {
          "name": "Data setup time",
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        {
          "name": "Data hold time",
          "symbol": "t6",
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          "min": 4,
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        {
          "name": "SYNC rising edge to SCLK falling edge",
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        {
          "name": "Minimum SYNC high time",
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          "min": 30,
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          "conditions": "",
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        {
          "name": "SCLK falling edge to LDAC falling edge",
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        {
          "name": "LDAC pulse width",
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          "name": "SCLK falling edge to LDAC rising edge",
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        {
          "name": "SCLK active edge to SDO valid",
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          "conditions": "strong SDO driver",
          "source_page": 5,
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        {
          "name": "SCLK active edge to SDO valid",
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          "kind": "timing",
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          "conditions": "weak SDO driver",
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          "source": "datasheet"
        },
        {
          "name": "CLR pulse width",
          "symbol": "t13",
          "kind": "timing",
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