AD5429YRUZ from Analog Devices, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	IOUT1A	output	DAC A current output.
2	IOUT2A	passive	DAC A analog ground, typically tied to system analog ground but can be biased to achieve single-supply operation.
3	RFBA	passive	DAC A feedback resistor pin that establishes voltage output by connecting to an external amplifier output.
4	VREFA	input	DAC A reference voltage input pin (reference input range ±10 V).
5	GND	power_in	Ground pin.
6	LDAC	input	Load DAC input allowing asynchronous update when low, or automatic synchronous update if held permanently low (on the 16th clock falling edge in standalone mode, or SYNC rising edge in daisy-chain mode).
7	SCLK	input	Serial clock input; data is clocked into the shift register on the falling edge by default, or on the rising edge via control bits.
8	SDIN	input	Serial data input; data is clocked into the 16-bit input register on the active edge of SCLK (falling edge by default).
9	SDO	output	Serial data output for daisy-chaining and DAC register readback, clocked out on the edge opposite to the one loading the shift register.
10	SYNC	input	Active-low frame synchronization input; when low it powers on the SCLK and DIN buffers and enables the input shift register, with data latched on the 16th active clock edge in standalone mode.
11	CLR	input	Active-low control input that clears the DAC output, input, and DAC registers, to zero scale or midscale as configured.
12	VDD	power_in	Positive power supply input, operating from 2.5 V to 5.5 V.
13	VREFB	input	DAC B reference voltage input pin (reference input range ±10 V).
14	RFBB	passive	DAC B feedback resistor pin that establishes voltage output by connecting to an external amplifier output.
15	IOUT2B	passive	DAC B analog ground, typically tied to system analog ground but can be biased to achieve single-supply operation.
16	IOUT1B	output	DAC B current output.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	TSSOP-16
Category	ADC/DAC/Data Conversion
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Relative Accuracy	INL	-0.5		0.5	LSB	AD5429	3
Differential Nonlinearity	DNL	-1		1	LSB	Guaranteed monotonic, AD5429	3
Gain Error		-25		25	mV		3
Output Leakage Current		-5		5	nA	Data = 0x0000, TA = 25°C, IOUT1	3
Output Leakage Current		-15		15	nA	Data = 0x0000, IOUT1	3
VREFA, VREFB Input Resistance		9	11	13	kΩ	Input resistance temperature coefficient = −50 ppm/°C	3
VREFA-to-VREFB Input Resistance Mismatch			1.6	2.5	%	Typical = 25°C, maximum = 125°C	3
Input Voltage High	VIH	1.7			V	VDD = 3.6 V to 5.5 V	3
Input Voltage Low	VIL			0.8	V	VDD = 2.7 V to 5.5 V	3
Input Voltage Low	VIL			0.7	V	VDD = 2.5 V to 2.7 V	3
Output Low Voltage	VOL			0.4	V	VDD = 4.5 V to 5.5 V, ISINK = 200 µA	3
Input Leakage Current	IIL			1	µA		3
Digital Input Capacitance			4	10	pF		3
Output Voltage Settling Time			80	120	ns	Measured to ±1 mV of FS	3
Output Voltage Settling Time			35	70	ns	Measured to ±4 mV of FS	3
Output Voltage Settling Time			30	60	ns	Measured to ±16 mV of FS	3
Digital Delay			20	40	ns		3
Output Capacitance			12	17	pF	DAC latches loaded with all 0s	4
Output Capacitance			25	30	pF	DAC latches loaded with all 1s	4
Power Supply Range	VDD	2.5		5.5	V		4
Supply Current	IDD		0.5	10	µA	TA = −40°C to +125°C, logic inputs = 0 V or VDD	4
Supply Current	IDD		0.7		µA	TA = 25°C, logic inputs = 0 V or VDD	4
Maximum clock frequency	fSCLK			50	MHz		5
SCLK cycle time	t1	20			ns		5
SCLK high time	t2	8			ns		5
SCLK low time	t3	8			ns		5
SYNC falling edge to SCLK falling edge setup time	t4	13			ns		5
Data setup time	t5	5			ns		5
Data hold time	t6	4			ns		5
SYNC rising edge to SCLK falling edge	t7	5			ns		5
Minimum SYNC high time	t8	30			ns		5
SCLK falling edge to LDAC falling edge	t9	0			ns		5
LDAC pulse width	t10	12			ns		5
SCLK falling edge to LDAC rising edge	t11	10			ns		5
SCLK active edge to SDO valid	t12	25			ns	strong SDO driver	5
SCLK active edge to SDO valid	t12	60			ns	weak SDO driver	5
CLR pulse width	t13	12			ns		5
SYNC rising edge to LDAC falling edge	t14	4.5			ns		5
VDD to GND	VDD	-0.3		7	V	TA = 25°C	7
VREFx, RFBx to GND		-12		12	V	TA = 25°C	7
IOUT1, IOUT2 to GND		-0.3		7	V	TA = 25°C	7
Input Current to Any Pin Except Supplies		-10		10	mA	TA = 25°C	7
Operating Temperature Range		-40		125	°C	Extended (Y Version)	7
Storage Temperature Range		-65		150	°C		7
Junction Temperature	TJ			150	°C		7
Lead Temperature, Soldering				300	°C	10 sec	7
IR Reflow, Peak Temperature				235	°C	<20 sec	7
Thermal Impedance	θJA		150		°C/W	16-Lead TSSOP	7

CAD (KiCad official)

Symbol: AD5429YRUZ
Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
3D model: TSSOP-16 (KiCad packages3D, STEP)
3D model files: ad5429yruz-etched.step / ad5429yruz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5429yruz.step / ad5429yruz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (28 pp, sha256 92e73915f7ff8583, retrieved 2026-10-31, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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AD5429YRUZ

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