component
AD5421BREZ-REEL7
Public Made by Adomby adom
Analog Devices Digital To Analog Converters (DAC), HTSSOP-28. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
"slug": "ad5421brez-reel7",
"version": "0.1.0",
"type": "component",
"description": "Analog Devices Digital To Analog Converters (DAC), HTSSOP-28. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"tags": [
"component",
"data acquisition",
"ad5421brez-reel7",
"factory-2.0.0",
"extractor-text"
],
"dependencies": {},
"hero": {
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"path": "docs/hero.png"
},
"files": [
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"component": {
"mpn": "AD5421BREZ-REEL7",
"manufacturer": "Analog Devices",
"package": "HTSSOP-28",
"pin_count": 29,
"category": "Data Acquisition",
"subcategory": "Digital To Analog Converters (DAC)",
"datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586194795853459456",
"parts": {
"symbol": "ad5421brez-reel7.kicad_sym",
"footprint": "ad5421brez-reel7.kicad_mod",
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"model_3d_step_plain": "ad5421brez-reel7.step",
"lbr": "ad5421brez-reel7.lbr"
},
"distributor_links": {
"lcsc": "C169543",
"digikey": "505-AD5421BREZ-REEL7TR-ND",
"mouser": "584-AD5421BREZ-R7"
},
"distributor_check": {
"checked_at": "2026-10-19T08:13:59Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": "505-AD5421BREZ-REEL7TR-ND",
"status": "found"
},
"mouser": {
"pn": "584-AD5421BREZ-R7",
"status": "found"
}
},
"pins": [
{
"number": "1",
"name": "IODVDD",
"type": "power_in",
"description": "Digital interface supply pin; the digital thresholds are referenced to the voltage applied here, which may be 1.71 V to 5.5 V relative to COM."
},
{
"number": "2",
"name": "SDO",
"type": "output",
"description": "Serial data output used to clock data out of the input shift register; data changes on the SCLK rising edge and is valid on the SCLK falling edge."
},
{
"number": "3",
"name": "SCLK",
"type": "input",
"description": "Serial clock input; data is read into the input shift register on the SCLK falling edge, with an operating clock rate of up to 30 MHz."
},
{
"number": "4",
"name": "SYNC",
"type": "input",
"description": "Active-low frame synchronization input; data is transferred on SCLK falling edges while SYNC is low, and the shift register data is latched on the SYNC rising edge."
},
{
"number": "5",
"name": "SDIN",
"type": "input",
"description": "Serial data input that must be valid on the SCLK falling edge."
},
{
"number": "6",
"name": "LDAC",
"type": "input",
"description": "Active-low load DAC input that updates the DAC register and output current; it must not be left floating, and if held permanently low the DAC register updates on the SYNC rising edge."
},
{
"number": "7",
"name": "FAULT",
"type": "output",
"description": "Active-high fault alarm output that goes high when a fault is detected (SPI failure, PEC error, loop current out of range, loop voltage low, or over-temperature)."
},
{
"number": "8",
"name": "DVDD",
"type": "power_out",
"description": "3.3 V digital supply output that must be decoupled to COM with 100 nF and 4.7 µF capacitors."
},
{
"number": "9",
"name": "ALARM_CURRENT_DIRECTION",
"type": "input",
"description": "Selects the alarm current direction: connect to DVDD for upper alarm current (22.8 mA/24 mA) or to COM for lower alarm current (3.2 mA)."
},
{
"number": "10",
"name": "RINT/REXT",
"type": "input",
"description": "Current-setting resistor select: connect to DVDD to use the internal current-setting resistor, or to COM to use an external resistor."
},
{
"number": "11",
"name": "RANGE0",
"type": "input",
"description": "Digital input that, together with RANGE1, selects the loop current range (connect to COM or DVDD per Table 9)."
},
{
"number": "12",
"name": "RANGE1",
"type": "input",
"description": "Digital input that, together with RANGE0, selects the loop current range (connect to COM or DVDD per Table 9)."
},
{
"number": "13",
"name": "COM",
"type": "power_in",
"description": "Ground reference pin for the AD5421; a 4.7 V Zener is recommended between LOOP- and COM for protection."
},
{
"number": "14",
"name": "COM",
"type": "power_in",
"description": "Ground reference pin for the AD5421, internally common with pin 13."
},
{
"number": "15",
"name": "REG_SEL2",
"type": "input",
"description": "Together with REG_SEL1 and REG_SEL0, selects the REGOUT regulator output voltage from 1.8 V to 12 V per Table 10."
},
{
"number": "16",
"name": "REG_SEL1",
"type": "input",
"description": "Together with REG_SEL2 and REG_SEL0, selects the REGOUT regulator output voltage from 1.8 V to 12 V per Table 10."
},
{
"number": "17",
"name": "REG_SEL0",
"type": "input",
"description": "Together with REG_SEL2 and REG_SEL1, selects the REGOUT regulator output voltage from 1.8 V to 12 V per Table 10."
},
{
"number": "18",
"name": "REFIN",
"type": "input",
"description": "Reference voltage input; 2.5 V is required for rated performance."
},
{
"number": "19",
"name": "REFOUT2",
"type": "output",
"description": "Internal 1.22 V reference output; a 100 nF capacitor between this pin and COM is recommended."
},
{
"number": "20",
"name": "REFOUT1",
"type": "output",
"description": "Internal 2.5 V reference output; a 100 nF capacitor between this pin and COM is recommended."
},
{
"number": "21",
"name": "CIN",
"type": "passive",
"description": "External slew-rate capacitor connection to COM for loop current slew control, and AC-coupled input for the HART FSK signal."
},
{
"number": "22",
"name": "REXT1",
"type": "passive",
"description": "External current-setting resistor connection; a precision 24 kΩ resistor may be connected between REXT1 and REXT2 to improve performance."
},
{
"number": "23",
"name": "REXT2",
"type": "passive",
"description": "External current-setting resistor connection; a precision 24 kΩ resistor may be connected between REXT1 and REXT2 to improve performance."
},
{
"number": "24",
"name": "LOOP-",
"type": "passive",
"description": "Loop current connection; the loop current is sensed between COM and LOOP- across the internal 52 Ω resistor, and the voltage at LOOP- is negative with respect to COM."
},
{
"number": "25",
"name": "VLOOP",
"type": "input",
"description": "Voltage monitor input accepting 0 V to 2.5 V, digitized to 8 bits for the fault register; a 20:1 divider allows monitoring of loop supply up to 50 V."
},
{
"number": "26",
"name": "DRIVE",
"type": "output",
"description": "Gate drive pin for an external depletion-mode MOSFET placed between the loop supply and REGIN."
},
{
"number": "27",
"name": "REGIN",
"type": "power_in",
"description": "Regulator input that accepts the loop voltage directly or through an external pass transistor; the rated input is 5.5 V to 52 V relative to LOOP-."
},
{
"number": "28",
"name": "REGOUT",
"type": "power_out",
"description": "Regulator output selectable from 1.8 V to 12 V via REG_SEL0-2; decouple to COM with more than 1 µF when driving a microconverter supply."
},
{
"number": "29",
"name": "EP",
"type": "passive",
"description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The TSSOP_EP package has an exposed pad (EPAD) that is not a numbered pin. The datasheet says it mus; Pin mapping was taken from Table 8 (TSSOP column, p.12-13) rather than the garbled text of the TSSOP; Types for these analog pins are not given as a KiCad class in the datasheet. I assigned passive base",
"exposed pad 29 added from the footprint"
],
"pages_sent": 30,
"cost_usd": 0.1762,
"at": "2026-10-19T08:12:08"
},
"datasheet": {
"url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586194795853459456",
"pages": 36,
"sha256": "d9214bebc999aeb6",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 29,
"described": 29,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
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},
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"units": "mm",
"origin": "footprint origin = pad-pattern centre",
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1.05
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"zmin_mm": 0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "ff242f1d3be9d09e7f929707a2c5b1ee974a4f882053b04bcdb1cd2cb21223ef",
"checked": "2026-10-19",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "ad5421brez-reel7-etched.step",
"role": "eda",
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"sha256": "e6b25cafee06d8440d4a752ccd80d6e24e579b59e36fcefdc3b24eeffe493410",
"checked": "2026-10-19",
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}
}