AD5328ARUZ-REEL7

{
  "slug": "ad5328aruz-reel7",
  "version": "0.1.0",
  "type": "component",
  "description": "Analog Devices Digital To Analog Converters (DAC), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "data acquisition",
    "ad5328aruz-reel7",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
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    "README.md",
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    "ad5328aruz-reel7.kicad_mod",
    "ad5328aruz-reel7.glb",
    "ad5328aruz-reel7.step",
    "ad5328aruz-reel7.lbr",
    "docs/hero.png",
    "docs/ad5328aruz-reel7-datasheet.pdf",
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    "ad5328aruz-reel7-hero.overlay.json",
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  "component": {
    "mpn": "AD5328ARUZ-REEL7",
    "manufacturer": "Analog Devices",
    "package": "TSSOP-16",
    "pin_count": 16,
    "category": "Data Acquisition",
    "subcategory": "Digital To Analog Converters (DAC)",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588886453455622144",
    "parts": {
      "symbol": "ad5328aruz-reel7.kicad_sym",
      "footprint": "ad5328aruz-reel7.kicad_mod",
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      "model_3d_plain": "ad5328aruz-reel7-etched.glb",
      "model_3d_step": "ad5328aruz-reel7-etched.step",
      "model_3d_step_plain": "ad5328aruz-reel7.step",
      "lbr": "ad5328aruz-reel7.lbr"
    },
    "distributor_links": {
      "lcsc": "C578185",
      "digikey": "505-AD5328ARUZ-REEL7TR-ND"
    },
    "distributor_check": {
      "checked_at": "2026-10-18T11:21:46Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "505-AD5328ARUZ-REEL7TR-ND",
        "status": "found"
      },
      "mouser": {
        "pn": null,
        "status": "quota"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "LDAC",
        "type": "input",
        "description": "Active-low control input that transfers the input register contents to the DAC registers, allowing simultaneous updates of all DAC outputs; it can alternatively be tied permanently low."
      },
      {
        "number": "2",
        "name": "SYNC",
        "type": "input",
        "description": "Active-low frame synchronization input that powers on the SCLK and DIN buffers and enables the input shift register, with data clocked in on the following 16 falling clock edges; if SYNC is taken high before the 16th falling edge the write sequence is ignored."
      },
      {
        "number": "3",
        "name": "VDD",
        "type": "power_in",
        "description": "Power supply input operable from 2.5 V to 5.5 V, to be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND."
      },
      {
        "number": "4",
        "name": "VOUTA",
        "type": "output",
        "description": "Buffered analog output voltage from DAC A, with rail-to-rail output amplifier operation."
      },
      {
        "number": "5",
        "name": "VOUTB",
        "type": "output",
        "description": "Buffered analog output voltage from DAC B, with rail-to-rail output amplifier operation."
      },
      {
        "number": "6",
        "name": "VOUTC",
        "type": "output",
        "description": "Buffered analog output voltage from DAC C, with rail-to-rail output amplifier operation."
      },
      {
        "number": "7",
        "name": "VOUTD",
        "type": "output",
        "description": "Buffered analog output voltage from DAC D, with rail-to-rail output amplifier operation."
      },
      {
        "number": "8",
        "name": "VREFABCD",
        "type": "input",
        "description": "Reference input for DACs A, B, C and D, with an input range of 0.25 V to VDD in unbuffered mode and 1 V to VDD in buffered mode."
      },
      {
        "number": "9",
        "name": "VREFEFGH",
        "type": "input",
        "description": "Reference input for DACs E, F, G and H, with an input range of 0.25 V to VDD in unbuffered mode and 1 V to VDD in buffered mode."
      },
      {
        "number": "10",
        "name": "VOUTE",
        "type": "output",
        "description": "Buffered analog output voltage from DAC E, with rail-to-rail output amplifier operation."
      },
      {
        "number": "11",
        "name": "VOUTF",
        "type": "output",
        "description": "Buffered analog output voltage from DAC F, with rail-to-rail output amplifier operation."
      },
      {
        "number": "12",
        "name": "VOUTG",
        "type": "output",
        "description": "Buffered analog output voltage from DAC G, with rail-to-rail output amplifier operation."
      },
      {
        "number": "13",
        "name": "VOUTH",
        "type": "output",
        "description": "Buffered analog output voltage from DAC H, with rail-to-rail output amplifier operation."
      },
      {
        "number": "14",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference point for all circuitry on the part."
      },
      {
        "number": "15",
        "name": "DIN",
        "type": "input",
        "description": "Serial data input to a 16-bit shift register, clocked in on the falling edge of SCLK; the input buffer is powered down after each write cycle."
      },
      {
        "number": "16",
        "name": "SCLK",
        "type": "input",
        "description": "Serial clock input on which data is clocked into the input shift register on the falling edge, supporting rates up to 30 MHz; the input buffer is powered down after each write cycle."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Pinout is taken from the Table 5 pin function list and Figure 3 on page 8, which covers the whole AD"
        ],
        "pages_sent": 10,
        "cost_usd": 0.0601,
        "at": "2026-10-18T11:18:39"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588886453455622144",
        "pages": 28,
        "sha256": "54d929c54190959e",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
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        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
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        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
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        "sha256": "6ad5e98224d02a427d9a6b929a28dbc158b9925fba5adec12db05079f1016948",
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        "sha256": "cc2b3d87c30ca2ab4868bedde81be9142f04e8718c26e672a020c1da5be9e497",
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}