component
AD5328ARUZ-REEL7
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Analog Devices Digital To Analog Converters (DAC), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownAD5328ARUZ-REEL7
Analog Devices · Digital To Analog Converters (DAC) · TSSOP-16
AD5328ARUZ-REEL7 from Analog Devices, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | LDAC | input | Active-low control input that transfers the input register contents to the DAC registers, allowing simultaneous updates of all DAC outputs; it can alternatively be tied permanently low. |
| 2 | SYNC | input | Active-low frame synchronization input that powers on the SCLK and DIN buffers and enables the input shift register, with data clocked in on the following 16 falling clock edges; if SYNC is taken high before the 16th falling edge the write sequence is ignored. |
| 3 | VDD | power_in | Power supply input operable from 2.5 V to 5.5 V, to be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. |
| 4 | VOUTA | output | Buffered analog output voltage from DAC A, with rail-to-rail output amplifier operation. |
| 5 | VOUTB | output | Buffered analog output voltage from DAC B, with rail-to-rail output amplifier operation. |
| 6 | VOUTC | output | Buffered analog output voltage from DAC C, with rail-to-rail output amplifier operation. |
| 7 | VOUTD | output | Buffered analog output voltage from DAC D, with rail-to-rail output amplifier operation. |
| 8 | VREFABCD | input | Reference input for DACs A, B, C and D, with an input range of 0.25 V to VDD in unbuffered mode and 1 V to VDD in buffered mode. |
| 9 | VREFEFGH | input | Reference input for DACs E, F, G and H, with an input range of 0.25 V to VDD in unbuffered mode and 1 V to VDD in buffered mode. |
| 10 | VOUTE | output | Buffered analog output voltage from DAC E, with rail-to-rail output amplifier operation. |
| 11 | VOUTF | output | Buffered analog output voltage from DAC F, with rail-to-rail output amplifier operation. |
| 12 | VOUTG | output | Buffered analog output voltage from DAC G, with rail-to-rail output amplifier operation. |
| 13 | VOUTH | output | Buffered analog output voltage from DAC H, with rail-to-rail output amplifier operation. |
| 14 | GND | power_in | Ground reference point for all circuitry on the part. |
| 15 | DIN | input | Serial data input to a 16-bit shift register, clocked in on the falling edge of SCLK; the input buffer is powered down after each write cycle. |
| 16 | SCLK | input | Serial clock input on which data is clocked into the input shift register on the falling edge, supporting rates up to 30 MHz; the input buffer is powered down after each write cycle. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSSOP-16 |
| Category | Data Acquisition |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Relative Accuracy (AD5328) | INL | -16 | 2 | 16 | LSB | 4 | |
| Differential Nonlinearity (AD5328) | DNL | -1 | 0.2 | 1 | LSB | Guaranteed monotonic by design over all codes | 4 |
| Offset Error | -60 | 5 | 60 | mV | VDD = 4.5 V, gain = 2, see Figure 27 and Figure 28 | 4 | |
| Gain Error | -1.25 | 0.3 | 1.25 | % of FSR | VDD = 4.5 V, gain = 2, see Figure 27 and Figure 28 | 4 | |
| Lower Deadband | 10 | 60 | mV | Lower deadband exists only if offset error is negative, see Figure 27 | 4 | ||
| Upper Deadband | 10 | 60 | mV | Upper deadband exists only if VREF = VDD and offset plus gain error is positive, see Figure 28 | 4 | ||
| VREF Input Range | VREF | 1 | V | Buffered reference mode | 4 | ||
| VREF Input Range | VREF | 0.25 | V | Unbuffered reference mode | 4 | ||
| VREF Input Impedance (RDAC) | RDAC | 10 | MΩ | Buffered reference mode and power-down mode | 4 | ||
| VREF Input Impedance (RDAC) | RDAC | 37 | 45 | kΩ | Unbuffered reference mode, 0 V to VREF output range | 4 | |
| VREF Input Impedance (RDAC) | RDAC | 18 | 22 | kΩ | Unbuffered reference mode, 0 V to 2 VREF output range | 4 | |
| Input Current | IIN | -1 | 1 | μA | 5 | ||
| Input Low Voltage | VIL | 0.8 | V | VDD = 5 V ± 10% | 5 | ||
| Input Low Voltage | VIL | 0.7 | V | VDD = 2.5 V | 5 | ||
| Input High Voltage | VIH | 1.7 | V | VDD = 2.5 V to 5.5 V, TTL and CMOS compatible | 5 | ||
| Supply Voltage | VDD | 2.5 | 5.5 | V | 5 | ||
| Normal Mode Supply Current | IDD | 1 | 1.8 | mA | VIH = VDD and VIL = GND; VDD = 4.5 V to 5.5 V; all DACs in unbuffered mode, in buffered mode | 5 | |
| Normal Mode Supply Current | IDD | 0.7 | 1.5 | mA | VIH = VDD and VIL = GND; VDD = 2.5 V to 3.6 V | 5 | |
| Power-Down Mode Supply Current | IDD | 0.4 | 1 | μA | VIH = VDD and VIL = GND; VDD = 4.5 V to 5.5 V | 5 | |
| Power-Down Mode Supply Current | IDD | 0.12 | 1 | μA | VIH = VDD and VIL = GND; VDD = 2.5 V to 3.6 V | 5 | |
| Output Voltage Settling Time (AD5328) | tS | 8 | 10 | μs | VREF = VDD = 5 V; 1/4 scale to 3/4 scale change (0x400 to 0xC00) | 5 | |
| SCLK cycle time | t1 | 33 | ns | SCLK cycle time | 6 | ||
| SCLK high time | t2 | 13 | ns | SCLK high time | 6 | ||
| SCLK low time | t3 | 13 | ns | SCLK low time | 6 | ||
| SYNC to SCLK falling edge setup time | t4 | 13 | ns | Temperature range (A, B version): −40°C to +105°C | 6 | ||
| SYNC to SCLK falling edge setup time | t4 | 15 | ns | Temperature range (A, B version): −40°C to +125°C | 6 | ||
| Data setup time | t5 | 5 | ns | Data set up time | 6 | ||
| Data hold time | t6 | 4.5 | ns | Data hold time | 6 | ||
| SCLK falling edge to SYNC rising edge | t7 | 0 | ns | SCLK falling edge to SYNC rising edge | 6 | ||
| Minimum SYNC high time | t8 | 50 | ns | Minimum SYNC high time | 6 | ||
| LDAC pulse width | t9 | 20 | ns | LDAC pulse width | 6 | ||
| SCLK falling edge to LDAC rising edge | t10 | 20 | ns | SCLK falling edge to LDAC rising edge | 6 | ||
| SCLK falling edge to LDAC falling edge | t11 | 0 | ns | SCLK falling edge to LDAC falling edge | 6 | ||
| VDD to GND | VDD | -0.3 | 7 | V | 7 | ||
| Digital Input Voltage to GND | -0.3 | V | Upper limit VDD + 0.3 V as printed | 7 | |||
| Reference Input Voltage to GND | -0.3 | V | Upper limit VDD + 0.3 V as printed | 7 | |||
| VOUTA-VOUTD to GND | VOUT | -0.3 | V | Upper limit VDD + 0.3 V as printed | 7 | ||
| Operating Temperature Range (Industrial, A Version) | TA | -40 | 125 | °C | 7 | ||
| Storage Temperature Range | TSTG | -65 | 150 | °C | 7 | ||
| Junction Temperature | TJ MAX | 150 | °C | 7 | |||
| Thermal Impedance, 16-Lead TSSOP | θJA | 150.4 | °C/W | 16-Lead TSSOP | 7 |
CAD (KiCad official)
- Symbol:
AD5328ARUZ-REEL7 - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
ad5328aruz-reel7-etched.step/ad5328aruz-reel7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad5328aruz-reel7.step/ad5328aruz-reel7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (28 pp, sha256
54d929c54190959e, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).