AD5324ARMZ-REEL7

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  "title": "AD5324ARMZ-REEL7",
  "brief": "Analog Devices Digital To Analog Converters (DAC), MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
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    "mpn": "AD5324ARMZ-REEL7",
    "manufacturer": "Analog Devices",
    "package": "MSOP-10",
    "pin_count": 10,
    "category": "Data Acquisition",
    "subcategory": "Digital To Analog Converters (DAC)",
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    "distributor_links": {
      "lcsc": "C578182",
      "digikey": "505-AD5324ARMZ-REEL7TR-ND"
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      {
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        "name": "VDD",
        "type": "power_in",
        "description": "Power supply input that can be operated from 2.5 V to 5.5 V and should be decoupled to GND."
      },
      {
        "number": "2",
        "name": "VOUTA",
        "type": "output",
        "description": "Buffered analog output voltage from DAC A, driven by a rail-to-rail output amplifier with output range 0 V to VREF."
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      {
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        "name": "VOUTB",
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        "description": "Buffered analog output voltage from DAC B, driven by a rail-to-rail output amplifier with output range 0 V to VREF."
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      {
        "number": "4",
        "name": "VOUTC",
        "type": "output",
        "description": "Buffered analog output voltage from DAC C, driven by a rail-to-rail output amplifier with output range 0 V to VREF."
      },
      {
        "number": "5",
        "name": "REFIN",
        "type": "input",
        "description": "Reference input for all four DACs with an input range from 0.25 V to VDD."
      },
      {
        "number": "6",
        "name": "VOUTD",
        "type": "output",
        "description": "Buffered analog output voltage from DAC D, driven by a rail-to-rail output amplifier with output range 0 V to VREF."
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        "name": "DIN",
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      {
        "number": "9",
        "name": "SCLK",
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        "description": "Serial clock input with data clocked on the falling edge, supporting clock speeds up to 30 MHz."
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      {
        "number": "10",
        "name": "SYNC",
        "type": "input",
        "description": "Active-low frame synchronization input that enables the shift register; if taken high before the 16th falling SCLK edge, the write sequence is ignored."
      }
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          "extractor flagged: Pin assignments are taken from the 10-Lead MSOP pin configuration (Figure 3) and Table 5 on page 7. "
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      "Package": "MSOP-10",
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          "name": "Power-Up Time",
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