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AD5324ARMZ-REEL7

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Analog Devices Digital To Analog Converters (DAC), MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AD5324ARMZ-REEL7

Analog Devices · Digital To Analog Converters (DAC) · MSOP-10

AD5324ARMZ-REEL7 from Analog Devices, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Power supply input that can be operated from 2.5 V to 5.5 V and should be decoupled to GND.
2 VOUTA output Buffered analog output voltage from DAC A, driven by a rail-to-rail output amplifier with output range 0 V to VREF.
3 VOUTB output Buffered analog output voltage from DAC B, driven by a rail-to-rail output amplifier with output range 0 V to VREF.
4 VOUTC output Buffered analog output voltage from DAC C, driven by a rail-to-rail output amplifier with output range 0 V to VREF.
5 REFIN input Reference input for all four DACs with an input range from 0.25 V to VDD.
6 VOUTD output Buffered analog output voltage from DAC D, driven by a rail-to-rail output amplifier with output range 0 V to VREF.
7 GND power_in Ground reference point for all circuitry on the part.
8 DIN input Serial data input to the 16-bit shift register, clocked in on the falling edge of SCLK, with the input buffer powered down after each write cycle.
9 SCLK input Serial clock input with data clocked on the falling edge, supporting clock speeds up to 30 MHz.
10 SYNC input Active-low frame synchronization input that enables the shift register; if taken high before the 16th falling SCLK edge, the write sequence is ignored.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package MSOP-10
Category Data Acquisition
Pins 10

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Relative Accuracy (INL) 2 16 LSB 3
Differential Nonlinearity 0.2 1 LSB Guaranteed monotonic by design over all codes 3
Offset Error -3 0.4 3 % of FSR See Figure 13 and Figure 14 3
Gain Error -1 0.15 1 % of FSR See Figure 13 and Figure 14 3
Lower Dead Band 20 60 mV Lower dead band exists only if offset error is negative 3
VREF Input Range VREF 0.25 V 3
VREF Input Impedance 37 45 kΩ Normal operation 3
VREF Input Impedance (power-down) 10 MΩ Power-down mode 3
Input Current -1 1 µA 4
VIL Input Low Voltage VIL 0.8 V VDD = 5 V ± 10% 4
VIL Input Low Voltage VIL 0.6 V VDD = 3 V ± 10% 4
VIL Input Low Voltage VIL 0.5 V VDD = 2.5 V 4
VIH Input High Voltage VIH 2.4 V VDD = 5 V ± 10% 4
VIH Input High Voltage VIH 2.1 V VDD = 3 V ± 10% 4
VIH Input High Voltage VIH 2 V VDD = 2.5 V 4
Supply voltage VDD 2.5 5.5 V 4
IDD Normal Mode IDD 600 900 µA VDD = 4.5 V to 5.5 V; VIH = VDD and VIL = GND 4
IDD Normal Mode IDD 500 700 µA VDD = 2.5 V to 3.6 V; VIH = VDD and VIL = GND 4
IDD Power-Down Mode IDD 0.2 1 µA VDD = 4.5 V to 5.5 V; VIH = VDD and VIL = GND 4
IDD Power-Down Mode IDD 0.08 1 µA VDD = 2.5 V to 3.6 V; VIH = VDD and VIL = GND 4
Output Voltage Settling Time 8 10 µs VREF = VDD = 5 V; ¼ scale to ¾ scale change (0x400 to 0xC00) 4
SCLK cycle time (t1) t1 40 ns VDD = 2.5 V to 3.6 V 5
SCLK cycle time (t1) t1 33 ns VDD = 3.6 V to 5.5 V 5
SCLK high time (t2) t2 16 ns VDD = 2.5 V to 3.6 V 5
SCLK high time (t2) t2 13 ns VDD = 3.6 V to 5.5 V 5
SCLK low time (t3) t3 16 ns VDD = 2.5 V to 3.6 V 5
SCLK low time (t3) t3 13 ns VDD = 3.6 V to 5.5 V 5
SYNC to SCLK falling edge setup time (t4) t4 16 ns VDD = 2.5 V to 3.6 V 5
SYNC to SCLK falling edge setup time (t4) t4 13 ns VDD = 3.6 V to 5.5 V 5
Data setup time (t5) t5 5 ns VDD = 2.5 V to 3.6 V 5
Data hold time (t6) t6 4.5 ns VDD = 2.5 V to 3.6 V 5
SCLK falling edge to SYNC rising edge (t7) t7 0 ns VDD = 2.5 V to 3.6 V 5
Minimum SYNC high time (t8) t8 80 ns VDD = 2.5 V to 3.6 V 5
Minimum SYNC high time (t8) t8 33 ns VDD = 3.6 V to 5.5 V 5
VDD to GND VDD -0.3 7 V 6
Operating Temperature Range -40 105 °C Industrial (A, B, W Version) 6
Storage Temperature Range -65 150 °C 6
Junction Temperature (TJ max) TJ 150 °C 6
Offset Error Drift -12 ppm of FSR/°C 3
Gain Error Drift -5 ppm of FSR/°C 3
DC Power Supply Rejection Ratio -60 dB ΔVDD = ±10% 3
DC Crosstalk 200 µV RL = 2 kΩ to GND or VDD 3
Reference Feedthrough -90 dB Frequency = 10 kHz 3
Minimum Output Voltage 0.001 V Measurement of the minimum and maximum drive capability of the output amplifier 3
DC Output Impedance 0.5 Ω 3
Short Circuit Current 25 mA VDD = 5 V 3
Short Circuit Current 16 mA VDD = 3 V 3
Power-Up Time 2.5 µs Coming out of power-down mode VDD = 5 V 3
Power-Up Time 5 µs Coming out of power-down mode VDD = 3 V 3
Pin Capacitance 3 pF 4
Slew Rate 0.7 V/µs 4
Major-Code Transition Glitch Energy 12 nV-sec 1 LSB change around major carry 4
Multiplying Bandwidth 200 kHz VREF = 2 V ± 0.1 V p-p 4
Total Harmonic Distortion -70 dB VREF = 2.5 V ± 0.1 V p-p; frequency = 10 kHz 4
Thermal Impedance, junction to ambient (10-Lead MSOP) θJA 206 °C/W 10-Lead MSOP 6
Thermal Impedance, junction to case (10-Lead MSOP) θJC 44 °C/W 10-Lead MSOP 6

CAD (KiCad official)

  • Symbol: AD5324ARMZ-REEL7
  • Footprint: Package_SO:MSOP-10_3x3mm_P0.5mm
  • 3D model: MSOP-10 (KiCad packages3D, STEP)
  • 3D model files: ad5324armz-reel7-etched.step / ad5324armz-reel7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5324armz-reel7.step / ad5324armz-reel7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (24 pp, sha256 bc06ab85376cc929, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF