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AD5293BRUZ-20-RL7
Public Made by Adomby adom
Analog Devices Digital Potentiometers, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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AD5293BRUZ-20-RL7
Analog Devices · Digital Potentiometers · TSSOP-14
AD5293BRUZ-20-RL7 from Analog Devices, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RESET | input | Hardware reset input; high logic transition sets RDAC register to midscale. |
| 2 | VSS | power_in | Negative supply pin; 0 V for single-supply or ±9 V to ±16.5 V for dual-supply applications. |
| 3 | A | passive | Terminal A of RDAC; operating voltage range VSS ≤ VA ≤ VDD. |
| 4 | W | passive | Wiper terminal W of RDAC; operating voltage range VSS ≤ VW ≤ VDD. |
| 5 | B | passive | Terminal B of RDAC; operating voltage range VSS ≤ VB ≤ VDD. |
| 6 | VDD | power_in | Positive power supply pin; 9 V to 33 V single-supply or ±9 V to ±16.5 V dual-supply. |
| 7 | EXT_CAP | passive | External capacitor pin; connect 1 µF capacitor with voltage rating ≥7 V. |
| 8 | VLOGIC | power_in | Logic power supply pin; operating range 2.7 V to 5.5 V. |
| 9 | GND | power_in | Logic ground reference pin; primary digital ground reference. |
| 10 | DIN | input | Serial data input; 16-bit shift register clocked on SCLK falling edge. |
| 11 | SCLK | input | Serial clock input; data transferred on falling edge at rates up to 50 MHz. |
| 12 | SYNC | input | Frame synchronization input; falling edge enables shift register, rising edge after 16th clock latches data. |
| 13 | SDO | tri_state | Serial data output; open-drain output for daisy-chain and readback mode operation. |
| 14 | RDY | tri_state | Ready pin; active-high open-drain output indicating completion of RDAC read/write operation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSSOP-14 |
| Category | Data Acquisition |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
AD5293BRUZ-20-RL7 - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
ad5293bruz-20-rl7-etched.step/ad5293bruz-20-rl7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad5293bruz-20-rl7.step/ad5293bruz-20-rl7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (24 pp, sha256
717f5791e0c7ebf3, retrieved 2026-09-22, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# AD5293BRUZ-20-RL7
**Analog Devices** · Digital Potentiometers · TSSOP-14
AD5293BRUZ-20-RL7 from Analog Devices, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RESET | input | Hardware reset input; high logic transition sets RDAC register to midscale. |
| 2 | VSS | power_in | Negative supply pin; 0 V for single-supply or ±9 V to ±16.5 V for dual-supply applications. |
| 3 | A | passive | Terminal A of RDAC; operating voltage range VSS ≤ VA ≤ VDD. |
| 4 | W | passive | Wiper terminal W of RDAC; operating voltage range VSS ≤ VW ≤ VDD. |
| 5 | B | passive | Terminal B of RDAC; operating voltage range VSS ≤ VB ≤ VDD. |
| 6 | VDD | power_in | Positive power supply pin; 9 V to 33 V single-supply or ±9 V to ±16.5 V dual-supply. |
| 7 | EXT_CAP | passive | External capacitor pin; connect 1 µF capacitor with voltage rating ≥7 V. |
| 8 | VLOGIC | power_in | Logic power supply pin; operating range 2.7 V to 5.5 V. |
| 9 | GND | power_in | Logic ground reference pin; primary digital ground reference. |
| 10 | DIN | input | Serial data input; 16-bit shift register clocked on SCLK falling edge. |
| 11 | SCLK | input | Serial clock input; data transferred on falling edge at rates up to 50 MHz. |
| 12 | SYNC | input | Frame synchronization input; falling edge enables shift register, rising edge after 16th clock latches data. |
| 13 | SDO | tri_state | Serial data output; open-drain output for daisy-chain and readback mode operation. |
| 14 | RDY | tri_state | Ready pin; active-high open-drain output indicating completion of RDAC read/write operation. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSSOP-14 |
| Category | Data Acquisition |
| Pins | 14 |
## CAD (KiCad official)
- Symbol: `AD5293BRUZ-20-RL7`
- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`
- 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files: `ad5293bruz-20-rl7-etched.step` / `ad5293bruz-20-rl7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad5293bruz-20-rl7.step` / `ad5293bruz-20-rl7.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588886283078393856) (24 pp, sha256 `717f5791e0c7ebf3`, retrieved 2026-09-22, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ad5293bruz-20-rl7-datasheet.pdf)