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Initial commit: component/ad5293bruz-20-rl7

Ray ·61af599b0a ·1mo ago
2 files changed +227
README.mdadded+50
@@ -0,0 +1,50 @@+# AD5293BRUZ-20-RL7++**Analog Devices** · Digital Potentiometers · TSSOP-14++AD5293BRUZ-20-RL7 from Analog Devices, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | RESET | input | Hardware reset input; high logic transition sets RDAC register to midscale. |+| 2 | VSS | power_in | Negative supply pin; 0 V for single-supply or ±9 V to ±16.5 V for dual-supply applications. |+| 3 | A | passive | Terminal A of RDAC; operating voltage range VSS ≤ VA ≤ VDD. |+| 4 | W | passive | Wiper terminal W of RDAC; operating voltage range VSS ≤ VW ≤ VDD. |+| 5 | B | passive | Terminal B of RDAC; operating voltage range VSS ≤ VB ≤ VDD. |+| 6 | VDD | power_in | Positive power supply pin; 9 V to 33 V single-supply or ±9 V to ±16.5 V dual-supply. |+| 7 | EXT_CAP | passive | External capacitor pin; connect 1 µF capacitor with voltage rating ≥7 V. |+| 8 | VLOGIC | power_in | Logic power supply pin; operating range 2.7 V to 5.5 V. |+| 9 | GND | power_in | Logic ground reference pin; primary digital ground reference. |+| 10 | DIN | input | Serial data input; 16-bit shift register clocked on SCLK falling edge. |+| 11 | SCLK | input | Serial clock input; data transferred on falling edge at rates up to 50 MHz. |+| 12 | SYNC | input | Frame synchronization input; falling edge enables shift register, rising edge after 16th clock latches data. |+| 13 | SDO | tri_state | Serial data output; open-drain output for daisy-chain and readback mode operation. |+| 14 | RDY | tri_state | Ready pin; active-high open-drain output indicating completion of RDAC read/write operation. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Analog Devices |+| Package | TSSOP-14 |+| Category | Data Acquisition |+| Pins | 14 |++## CAD (KiCad official)++- Symbol: `AD5293BRUZ-20-RL7`+- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`+- 3D model: TSSOP-14 (KiCad packages3D, STEP)+- 3D model files: `ad5293bruz-20-rl7-etched.step` / `ad5293bruz-20-rl7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad5293bruz-20-rl7.step` / `ad5293bruz-20-rl7.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588886283078393856) (24 pp, sha256 `717f5791e0c7ebf3`, retrieved 2026-09-22, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ad5293bruz-20-rl7-datasheet.pdf)
page.jsonadded+177
@@ -0,0 +1,177 @@+{+  "slug": "ad5293bruz-20-rl7",+  "version": "0.1.0",+  "type": "component",+  "description": "Analog Devices Digital Potentiometers, TSSOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "data acquisition",+    "ad5293bruz-20-rl7",+    "factory-2.0.0",+    "extractor-text"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "ad5293bruz-20-rl7.kicad_sym",+    "ad5293bruz-20-rl7.kicad_mod",+    "ad5293bruz-20-rl7.glb",+    "ad5293bruz-20-rl7.step",+    "ad5293bruz-20-rl7.lbr",+    "docs/hero.png",+    "docs/ad5293bruz-20-rl7-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "component": {+    "mpn": "AD5293BRUZ-20-RL7",+    "manufacturer": "Analog Devices",+    "package": "TSSOP-14",+    "pin_count": 14,+    "category": "Data Acquisition",+    "subcategory": "Digital Potentiometers",+    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588886283078393856",+    "parts": {+      "symbol": "ad5293bruz-20-rl7.kicad_sym",+      "footprint": "ad5293bruz-20-rl7.kicad_mod",+      "model_3d": "ad5293bruz-20-rl7-etched.glb",+      "model_3d_plain": "ad5293bruz-20-rl7.glb",+      "model_3d_step": "ad5293bruz-20-rl7-etched.step",+      "model_3d_step_plain": "ad5293bruz-20-rl7.step",+      "lbr": "ad5293bruz-20-rl7.lbr"+    },+    "distributor_links": {+      "lcsc": "C444343"+    },+    "pins": [+      {+        "number": "1",+        "name": "RESET",+        "type": "input",+        "description": "Hardware reset input; high logic transition sets RDAC register to midscale."+      },+      {+        "number": "2",+        "name": "VSS",+        "type": "power_in",+        "description": "Negative supply pin; 0 V for single-supply or ±9 V to ±16.5 V for dual-supply applications."+      },+      {+        "number": "3",+        "name": "A",+        "type": "passive",+        "description": "Terminal A of RDAC; operating voltage range VSS ≤ VA ≤ VDD."+      },+      {+        "number": "4",+        "name": "W",+        "type": "passive",+        "description": "Wiper terminal W of RDAC; operating voltage range VSS ≤ VW ≤ VDD."+      },+      {+        "number": "5",+        "name": "B",+        "type": "passive",+        "description": "Terminal B of RDAC; operating voltage range VSS ≤ VB ≤ VDD."+      },+      {+        "number": "6",+        "name": "VDD",+        "type": "power_in",+        "description": "Positive power supply pin; 9 V to 33 V single-supply or ±9 V to ±16.5 V dual-supply."+      },+      {+        "number": "7",+        "name": "EXT_CAP",+        "type": "passive",+        "description": "External capacitor pin; connect 1 µF capacitor with voltage rating ≥7 V."+      },+      {+        "number": "8",+        "name": "VLOGIC",+        "type": "power_in",+        "description": "Logic power supply pin; operating range 2.7 V to 5.5 V."+      },+      {+        "number": "9",+        "name": "GND",+        "type": "power_in",+        "description": "Logic ground reference pin; primary digital ground reference."+      },+      {+        "number": "10",+        "name": "DIN",+        "type": "input",+        "description": "Serial data input; 16-bit shift register clocked on SCLK falling edge."+      },+      {+        "number": "11",+        "name": "SCLK",+        "type": "input",+        "description": "Serial clock input; data transferred on falling edge at rates up to 50 MHz."+      },+      {+        "number": "12",+        "name": "SYNC",+        "type": "input",+        "description": "Frame synchronization input; falling edge enables shift register, rising edge after 16th clock latches data."+      },+      {+        "number": "13",+        "name": "SDO",+        "type": "tri_state",+        "description": "Serial data output; open-drain output for daisy-chain and readback mode operation."+      },+      {+        "number": "14",+        "name": "RDY",+        "type": "tri_state",+        "description": "Ready pin; active-high open-drain output indicating completion of RDAC read/write operation."+      }+    ],+    "provenance": {+      "extractor": "extract_pins 0.2",+      "factory_chain": {+        "factory": "2.0.0",+        "extractor": "extract_pins 0.2",+        "primary_model": "claude-haiku-4-5-20251001",+        "primary_mode": "text",+        "consensus_model": "claude-sonnet-4-6",+        "consensus": "agreed",+        "guards": "pin_guards 0.1: passed",+        "guard_notes": [],+        "pages_sent": 24,+        "cost_usd": 0.2536,+        "at": "2026-09-22T03:00:20"+      },+      "datasheet": {+        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588886283078393856",+        "pages": 24,+        "sha256": "717f5791e0c7ebf3",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 14,+        "described": 14,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "visibility": "public",+  "org": "adom",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file