component
AD5206BRUZ50-REEL7
Public Made by Adomby adom
Analog Devices Digital Potentiometers, TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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AD5206BRUZ50-REEL7
Analog Devices · Digital Potentiometers · TSSOP-24
AD5206BRUZ50-REEL7 from Analog Devices, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A6 | passive | Terminal A of RDAC 6, a resistor terminal with voltage range VSS to VDD. |
| 2 | W6 | passive | Wiper of RDAC 6, addressed as 101 (decoded per Table 12) and bounded by the VSS to VDD resistor-terminal voltage range. |
| 3 | B6 | passive | Terminal B of RDAC 6, a resistor terminal with voltage range VSS to VDD. |
| 4 | GND | power_in | Digital ground reference for the logic levels of CS, SDI, and CLK. |
| 5 | CS | input | Active-low chip select; when CS returns high, the serial register data is decoded by the address bits and loaded into the target RDAC latch. |
| 6 | VDD | power_in | Positive power supply specified for operation at both 3 V and 5 V, with |
| 7 | SDI | input | Serial data input; data is entered MSB first. |
| 8 | CLK | input | Serial clock input, positive-edge triggered. |
| 9 | VSS | power_in | Negative power supply specified for operation at both 0 V and −2.7 V, with |
| 10 | B5 | passive | Terminal B of RDAC 5, a resistor terminal with voltage range VSS to VDD. |
| 11 | W5 | passive | Wiper of RDAC 5, addressed as 100 (decoded per Table 12) and bounded by the VSS to VDD resistor-terminal voltage range. |
| 12 | A5 | passive | Terminal A of RDAC 5, a resistor terminal with voltage range VSS to VDD. |
| 13 | B3 | passive | Terminal B of RDAC 3, a resistor terminal with voltage range VSS to VDD. |
| 14 | W3 | passive | Wiper of RDAC 3, addressed as 010 (decoded per Table 12) and bounded by the VSS to VDD resistor-terminal voltage range. |
| 15 | A3 | passive | Terminal A of RDAC 3, a resistor terminal with voltage range VSS to VDD. |
| 16 | B1 | passive | Terminal B of RDAC 1, a resistor terminal with voltage range VSS to VDD. |
| 17 | W1 | passive | Wiper of RDAC 1, addressed as 000 (decoded per Table 12) and bounded by the VSS to VDD resistor-terminal voltage range. |
| 18 | A1 | passive | Terminal A of RDAC 1, a resistor terminal with voltage range VSS to VDD. |
| 19 | A2 | passive | Terminal A of RDAC 2, a resistor terminal with voltage range VSS to VDD. |
| 20 | W2 | passive | Wiper of RDAC 2, addressed as 001 (decoded per Table 12) and bounded by the VSS to VDD resistor-terminal voltage range. |
| 21 | B2 | passive | Terminal B of RDAC 2, a resistor terminal with voltage range VSS to VDD. |
| 22 | A4 | passive | Terminal A of RDAC 4, a resistor terminal with voltage range VSS to VDD. |
| 23 | W4 | passive | Wiper of RDAC 4, addressed as 011 (decoded per Table 12) and bounded by the VSS to VDD resistor-terminal voltage range. |
| 24 | B4 | passive | Terminal B of RDAC 4, a resistor terminal with voltage range VSS to VDD. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSSOP-24 |
| Category | ADC/DAC/Data Conversion |
| Pins | 24 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Resistor Differential NL (R-DNL) | R-DNL | -1 | 0.25 | 1 | LSB | RWB, VA = no connect | 3 |
| Resistor Nonlinearity Error (R-INL) | R-INL | -2 | 0.5 | 2 | LSB | RWB, VA = no connect | 3 |
| Nominal Resistor Tolerance | ΔRAB | -30 | 30 | % | TA = 25°C | 3 | |
| Nominal Resistance Match | ΔR/RAB | 0.25 | 1.5 | % | Channel 1 to Channel 2, Channel 3, and Channel 4, or to Channel 5 and Channel 6; VAB = VDD | 3 | |
| Wiper Resistance | RW | 50 | 100 | Ω | IW = 1 V/R, VDD = 5 V | 3 | |
| Differential Nonlinearity (DNL) | DNL | -1 | 0.25 | 1 | LSB | 3 | |
| Integral Nonlinearity (INL) | INL | -2 | 0.5 | 2 | LSB | 3 | |
| Full-Scale Error | VWFSE | -2 | -1 | 0 | LSB | Code = full scale | 3 |
| Zero-Scale Error | VWZSE | 0 | 1 | 2 | LSB | Code = zero scale | 3 |
| Shutdown Current | IA_SD | 0.01 | 5 | μA | 3 | ||
| Common-Mode Leakage | ICM | 1 | nA | VA = VB = VW = 0, VDD = +2.7 V, VSS = −2.5 V | 3 | ||
| Input Logic High | VIH | 2.4 | V | VDD = 5 V | 3 | ||
| Input Logic High | VIH | 2.1 | V | VDD = 3 V | 3 | ||
| Input Logic Low | VIL | 0.8 | V | VDD = 5 V | 3 | ||
| Input Logic Low | VIL | 0.6 | V | VDD = 3 V | 3 | ||
| Output Logic High | VOH | 4.9 | V | RPULL-UP = 1 kΩ to 5 V | 3 | ||
| Output Logic Low | VOL | 0.4 | V | IOL = 1.6 mA, VLOGIC = 5 V | 3 | ||
| Input Current | IIL | -1 | 1 | μA | VIN = 0 V or 5 V | 3 | |
| Power Single-Supply Range | VDD | 2.7 | 5.5 | V | VSS = 0 V | 3 | |
| Power Dual-Supply Range | VDD/VSS | 2.3 | 2.7 | V | 3 | ||
| Positive Supply Current | IDD | 12 | 60 | μA | VIH = 5 V or VIL = 0 V | 3 | |
| Negative Supply Current | ISS | 12 | 60 | μA | VSS = −2.5 V, VDD = +2.7 V | 3 | |
| Power Supply Sensitivity | PSS | 0.0002 | 0.005 | %/% | ΔVDD = 5 V ± 10% | 3 | |
| Input Clock Pulse Width | tCH, tCL | 20 | ns | Clock level high or low | 4 | ||
| Data Setup Time | tDS | 5 | ns | 4 | |||
| Data Hold Time | tDH | 5 | ns | 4 | |||
| CLK-to-SDO Propagation Delay | tPD | 150 | ns | RL = 2 kΩ, CL < 20 pF | 4 | ||
| Setup Time | tCSS | 15 | ns | 4 | |||
| CS High Pulse Width | tCSW | 40 | ns | 4 | |||
| Reset Pulse Width | tRS | 90 | ns | 4 | |||
| CLK Fall to CS Fall Setup | tCSH0 | 0 | ns | 4 | |||
| CLK Fall to CS Rise Hold Time | tCSH1 | 0 | ns | 4 | |||
| CS Rise to Clock Rise Setup | tCS1 | 10 | ns | 4 | |||
| VDD to GND | VDD | -0.3 | 7 | V | 6 | ||
| VSS to GND | VSS | -7 | 0 | V | 6 | ||
| VDD to VSS | VDD/VSS | 7 | V | 6 | |||
| Pulsed Terminal Current | IA, IB, IW | -20 | 20 | mA | Pulsed | 6 | |
| Continuous Terminal Current | IA, IB, IW | -2.5 | 2.5 | mA | Continuous, 50 kΩ and 100 kΩ end-to-end resistance | 6 | |
| Digital Input and Output Voltage to GND | -0.3 | V | 6 | ||||
| Operating Temperature Range | TA | -40 | 85 | °C | 6 | ||
| Maximum Junction Temperature | TJ max | 150 | °C | 6 | |||
| Storage Temperature | -65 | 150 | °C | 6 | |||
| Reflow Soldering Peak Temperature | 260 | °C | Peak temperature | 6 | |||
| Time at Peak Temperature | 20 | 40 | sec | 6 | |||
| Nominal End-to-End Resistance | RAB | 50 | kΩ | 1 | |||
| Resistance Temperature Coefficient | ΔRAB/ΔT | 700 | ppm/°C | VAB = VDD, wiper = no connect | 3 | ||
| Voltage Divider Temperature Coefficient | ΔVW/ΔT | 15 | ppm/°C | Code = midscale | 3 | ||
| Junction-to-Ambient Thermal Resistance (24-Lead TSSOP) | θJA | 82.76 | °C/W | JEDEC natural convection environment | 6 | ||
| Junction-to-Board Thermal Resistance (24-Lead TSSOP) | θJB | 37.06 | °C/W | JEDEC θJB environment | 6 |
CAD (KiCad official)
- Symbol:
AD5206BRUZ50-REEL7 - Footprint:
Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm - 3D model: TSSOP-24 (KiCad packages3D, STEP)
- 3D model files:
ad5206bruz50-reel7-etched.step/ad5206bruz50-reel7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad5206bruz50-reel7.step/ad5206bruz50-reel7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (16 pp, sha256
d394eb4fd3679cbf, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).