component
AD5174BRMZ-10
Public Made by Adomby adom
Analog Devices Digital Potentiometers, MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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AD5174BRMZ-10
Analog Devices · Digital Potentiometers · MSOP-10
AD5174BRMZ-10 from Analog Devices, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Positive power supply (2.7 V to 5.5 V single supply), to be decoupled with 0.1 μF ceramic and 10 μF capacitors. |
| 2 | A | passive | Terminal A of the RDAC, with voltage range VSS ≤ VA ≤ VDD. |
| 3 | W | passive | Wiper terminal of the RDAC, with voltage range VSS ≤ VW ≤ VDD. |
| 4 | VSS | power_in | Negative supply, connected to 0 V for single-supply applications and decoupled with 0.1 μF ceramic and 10 μF capacitors. |
| 5 | EXT_CAP | passive | External capacitor pin: connect a 1 μF capacitor (voltage rating ≥7 V) between EXT_CAP and VSS. |
| 6 | GND | power_in | Ground pin, logic ground reference. |
| 7 | SDO | output | Serial data output for daisy-chain or readback mode; open-drain output that requires an external pull-up resistor even if not used. |
| 8 | DIN | input | Serial data line used with SCLK to clock data into or out of the 16-bit input register. |
| 9 | SCLK | input | Serial clock input; data is clocked into the shift register on the falling edge, at rates up to 50 MHz. |
| 10 | SYNC | input | Falling-edge frame synchronization signal; when low it enables the shift register, and the selected register updates on the SYNC rising edge after the 16th clock cycle. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | MSOP-10 |
| Category | Data Converters |
| Pins | 10 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Nominal Resistance | RAB | 10 | kΩ | 10 kΩ nominal, AD5174BRMZ-10 | 1 | ||
| Nominal Resistor Tolerance | -15 | 15 | % | 3 | |||
| Resistance Temperature Coefficient | 35 | ppm/°C | Code = full scale | 3 | |||
| Resistor Integral Nonlinearity | R-INL | -1 | 1 | LSB | /VDD − VSS/ = 3.6 V to 5.5 V | 3 | |
| Resistor Integral Nonlinearity | R-INL | -1 | 1.5 | LSB | /VDD − VSS/ = 3.3 V to 3.6 V | 3 | |
| Resistor Integral Nonlinearity | R-INL | -2.5 | 2.5 | LSB | /VDD − VSS/ = 2.7 V to 3.3 V | 3 | |
| Resistor Differential Nonlinearity | R-DNL | -1 | 1 | LSB | 3 | ||
| Wiper Resistance | RW | 35 | 70 | Ω | Code = zero scale | 3 | |
| Input Logic High | VINH | 2 | V | 3 | |||
| Input Logic Low | VINL | 0.8 | V | 3 | |||
| Input Current | IIN | -1 | 1 | μA | 3 | ||
| Output Voltage Low | VOL | 0.4 | V | RPULL_UP = 2.2 kΩ to VDD, VDD = 2.7 V to 5.5 V, VSS = 0 V | 3 | ||
| Output Voltage Low | VOL | 0.6 | V | RPULL_UP = 2.2 kΩ to VDD, VDD = 2.5 V to 2.75 V, VSS = −2.5 V to −2.75 V | 3 | ||
| Tristate Leakage Current | -1 | 1 | μA | 3 | |||
| Single-Supply Power Range | VDD | 2.7 | 5.5 | V | VSS = 0 V | 3 | |
| Supply Current Positive | IDD | 1 | μA | 3 | |||
| Supply Current Negative | ISS | -1 | μA | 3 | |||
| 50-TP Store Current Positive | IDD_OTP_STORE | 4 | mA | 3 | |||
| 50-TP Store Current Negative | ISS_OTP_STORE | -4 | mA | 3 | |||
| 50-TP Read Current Positive | IDD_OTP_READ | 500 | μA | 3 | |||
| 50-TP Read Current Negative | ISS_OTP_READ | -500 | μA | 3 | |||
| Power Dissipation | PDISS | 5.5 | μW | VIH = VDD or VIL = GND | 3 | ||
| Power Supply Rejection Ratio | PSRR | -55 | -50 | dB | ΔVDD/ΔVSS = ±5 V ± 10% | 3 | |
| SCLK cycle time | t1 | 20 | ns | 4 | |||
| SCLK high time | t2 | 10 | ns | 4 | |||
| SCLK low time | t3 | 10 | ns | 4 | |||
| SYNC to SCLK falling edge setup time | t4 | 15 | ns | 4 | |||
| Data setup time | t5 | 5 | ns | 4 | |||
| Data hold time | t6 | 5 | ns | 4 | |||
| SCLK falling edge to SYNC rising edge | t7 | 1 | ns | 4 | |||
| Minimum SYNC high time | t8 | 400 | ns | 4 | |||
| SYNC rising edge to next SCLK fall ignored | t9 | 15 | ns | 4 | |||
| SCLK rising edge to SDO valid | t10 | 450 | ns | RPULL_UP = 2.2 kΩ to VDD, capacitance load of 168 pF | 4 | ||
| Memory readback execute time | tMEMORY_READ | 6 | μs | 4 | |||
| Memory program time | tMEMORY_PROGRAM | 350 | ms | 4 | |||
| Reset OTP restore time | tRESET | 600 | μs | 4 | |||
| Power-on 50-TP restore time | tPOWER-UP | 2 | ms | Maximum time after VDD − VSS is equal to 2.5 V | 4 | ||
| VDD to GND | VDD | -0.3 | 7 | V | TA = 25°C | 6 | |
| VSS to GND | VSS | -7 | 0.3 | V | TA = 25°C | 6 | |
| VDD to VSS | 7 | V | TA = 25°C | 6 | |||
| Digital Input and Output Voltage to GND | -0.3 | V | Upper limit VDD + 0.3 V | 6 | |||
| EXT_CAP to VSS | 7 | V | TA = 25°C | 6 | |||
| IA, IW Continuous | IA, IW | -6 | 6 | mA | Continuous | 6 | |
| Operating Temperature Range | -40 | 125 | °C | Includes programming of 50-TP memory | 6 | ||
| Maximum Junction Temperature | TJ max | 150 | °C | 6 | |||
| Storage Temperature Range | -65 | 150 | °C | 6 | |||
| Reflow Peak Temperature | 260 | °C | Time at peak 20 sec to 40 sec | 6 | |||
| Thermal Resistance Junction to Ambient, 10-Lead MSOP | θJA | 135 | °C/W | JEDEC 2S2P test board, still air | 6 | ||
| Capacitance A | 90 | pF | f = 1 MHz, measured to GND, code = half scale | 3 | |||
| Capacitance W | 40 | pF | f = 1 MHz, measured to GND, code = half scale | 3 | |||
| Common-Mode Leakage Current | 50 | nA | VA = VW | 3 | |||
| Input Capacitance | CIN | 5 | pF | 3 | |||
| Output Capacitance | 5 | pF | 3 | ||||
| Bandwidth | 700 | kHz | −3 dB, RAW = 5 kΩ, Terminal W, see Figure 24 | 4 | |||
| Total Harmonic Distortion | -90 | dB | VA = 1 V rms, f = 1 kHz, RAW = 5 kΩ | 4 | |||
| Resistor Noise Density | 13 | nV/√Hz | RWB = 5 kΩ, TA = 25°C, f = 10 kHz | 4 |
CAD (KiCad official)
- Symbol:
AD5174BRMZ-10 - Footprint:
Package_SO:MSOP-10_3x3mm_P0.5mm - 3D model: MSOP-10 (KiCad packages3D, STEP)
- 3D model files:
ad5174brmz-10-etched.step/ad5174brmz-10-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad5174brmz-10.step/ad5174brmz-10.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (20 pp, sha256
9aad1c62688bcde2, retrieved 2026-10-31, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# AD5174BRMZ-10
**Analog Devices** · Digital Potentiometers · MSOP-10
AD5174BRMZ-10 from Analog Devices, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Positive power supply (2.7 V to 5.5 V single supply), to be decoupled with 0.1 μF ceramic and 10 μF capacitors. |
| 2 | A | passive | Terminal A of the RDAC, with voltage range VSS ≤ VA ≤ VDD. |
| 3 | W | passive | Wiper terminal of the RDAC, with voltage range VSS ≤ VW ≤ VDD. |
| 4 | VSS | power_in | Negative supply, connected to 0 V for single-supply applications and decoupled with 0.1 μF ceramic and 10 μF capacitors. |
| 5 | EXT_CAP | passive | External capacitor pin: connect a 1 μF capacitor (voltage rating ≥7 V) between EXT_CAP and VSS. |
| 6 | GND | power_in | Ground pin, logic ground reference. |
| 7 | SDO | output | Serial data output for daisy-chain or readback mode; open-drain output that requires an external pull-up resistor even if not used. |
| 8 | DIN | input | Serial data line used with SCLK to clock data into or out of the 16-bit input register. |
| 9 | SCLK | input | Serial clock input; data is clocked into the shift register on the falling edge, at rates up to 50 MHz. |
| 10 | SYNC | input | Falling-edge frame synchronization signal; when low it enables the shift register, and the selected register updates on the SYNC rising edge after the 16th clock cycle. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | MSOP-10 |
| Category | Data Converters |
| Pins | 10 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Nominal Resistance | RAB | | 10 | | kΩ | 10 kΩ nominal, AD5174BRMZ-10 | 1 |
| Nominal Resistor Tolerance | | -15 | | 15 | % | | 3 |
| Resistance Temperature Coefficient | | | 35 | | ppm/°C | Code = full scale | 3 |
| Resistor Integral Nonlinearity | R-INL | -1 | | 1 | LSB | /VDD − VSS/ = 3.6 V to 5.5 V | 3 |
| Resistor Integral Nonlinearity | R-INL | -1 | | 1.5 | LSB | /VDD − VSS/ = 3.3 V to 3.6 V | 3 |
| Resistor Integral Nonlinearity | R-INL | -2.5 | | 2.5 | LSB | /VDD − VSS/ = 2.7 V to 3.3 V | 3 |
| Resistor Differential Nonlinearity | R-DNL | -1 | | 1 | LSB | | 3 |
| Wiper Resistance | RW | | 35 | 70 | Ω | Code = zero scale | 3 |
| Input Logic High | VINH | 2 | | | V | | 3 |
| Input Logic Low | VINL | | | 0.8 | V | | 3 |
| Input Current | IIN | -1 | | 1 | μA | | 3 |
| Output Voltage Low | VOL | | | 0.4 | V | RPULL_UP = 2.2 kΩ to VDD, VDD = 2.7 V to 5.5 V, VSS = 0 V | 3 |
| Output Voltage Low | VOL | | | 0.6 | V | RPULL_UP = 2.2 kΩ to VDD, VDD = 2.5 V to 2.75 V, VSS = −2.5 V to −2.75 V | 3 |
| Tristate Leakage Current | | -1 | | 1 | μA | | 3 |
| Single-Supply Power Range | VDD | 2.7 | | 5.5 | V | VSS = 0 V | 3 |
| Supply Current Positive | IDD | | | 1 | μA | | 3 |
| Supply Current Negative | ISS | -1 | | | μA | | 3 |
| 50-TP Store Current Positive | IDD_OTP_STORE | | | 4 | mA | | 3 |
| 50-TP Store Current Negative | ISS_OTP_STORE | -4 | | | mA | | 3 |
| 50-TP Read Current Positive | IDD_OTP_READ | | | 500 | μA | | 3 |
| 50-TP Read Current Negative | ISS_OTP_READ | -500 | | | μA | | 3 |
| Power Dissipation | PDISS | | | 5.5 | μW | VIH = VDD or VIL = GND | 3 |
| Power Supply Rejection Ratio | PSRR | | -55 | -50 | dB | ΔVDD/ΔVSS = ±5 V ± 10% | 3 |
| SCLK cycle time | t1 | 20 | | | ns | | 4 |
| SCLK high time | t2 | 10 | | | ns | | 4 |
| SCLK low time | t3 | 10 | | | ns | | 4 |
| SYNC to SCLK falling edge setup time | t4 | 15 | | | ns | | 4 |
| Data setup time | t5 | 5 | | | ns | | 4 |
| Data hold time | t6 | 5 | | | ns | | 4 |
| SCLK falling edge to SYNC rising edge | t7 | 1 | | | ns | | 4 |
| Minimum SYNC high time | t8 | 400 | | | ns | | 4 |
| SYNC rising edge to next SCLK fall ignored | t9 | 15 | | | ns | | 4 |
| SCLK rising edge to SDO valid | t10 | | | 450 | ns | RPULL_UP = 2.2 kΩ to VDD, capacitance load of 168 pF | 4 |
| Memory readback execute time | tMEMORY_READ | | | 6 | μs | | 4 |
| Memory program time | tMEMORY_PROGRAM | | | 350 | ms | | 4 |
| Reset OTP restore time | tRESET | | | 600 | μs | | 4 |
| Power-on 50-TP restore time | tPOWER-UP | | | 2 | ms | Maximum time after VDD − VSS is equal to 2.5 V | 4 |
| VDD to GND | VDD | -0.3 | | 7 | V | TA = 25°C | 6 |
| VSS to GND | VSS | -7 | | 0.3 | V | TA = 25°C | 6 |
| VDD to VSS | | | | 7 | V | TA = 25°C | 6 |
| Digital Input and Output Voltage to GND | | -0.3 | | | V | Upper limit VDD + 0.3 V | 6 |
| EXT_CAP to VSS | | | | 7 | V | TA = 25°C | 6 |
| IA, IW Continuous | IA, IW | -6 | | 6 | mA | Continuous | 6 |
| Operating Temperature Range | | -40 | | 125 | °C | Includes programming of 50-TP memory | 6 |
| Maximum Junction Temperature | TJ max | | | 150 | °C | | 6 |
| Storage Temperature Range | | -65 | | 150 | °C | | 6 |
| Reflow Peak Temperature | | | | 260 | °C | Time at peak 20 sec to 40 sec | 6 |
| Thermal Resistance Junction to Ambient, 10-Lead MSOP | θJA | | 135 | | °C/W | JEDEC 2S2P test board, still air | 6 |
| Capacitance A | | | 90 | | pF | f = 1 MHz, measured to GND, code = half scale | 3 |
| Capacitance W | | | 40 | | pF | f = 1 MHz, measured to GND, code = half scale | 3 |
| Common-Mode Leakage Current | | | 50 | | nA | VA = VW | 3 |
| Input Capacitance | CIN | | 5 | | pF | | 3 |
| Output Capacitance | | | 5 | | pF | | 3 |
| Bandwidth | | | 700 | | kHz | −3 dB, RAW = 5 kΩ, Terminal W, see Figure 24 | 4 |
| Total Harmonic Distortion | | | -90 | | dB | VA = 1 V rms, f = 1 kHz, RAW = 5 kΩ | 4 |
| Resistor Noise Density | | | 13 | | nV/√Hz | RWB = 5 kΩ, TA = 25°C, f = 10 kHz | 4 |
## CAD (KiCad official)
- Symbol: `AD5174BRMZ-10`
- Footprint: `Package_SO:MSOP-10_3x3mm_P0.5mm`
- 3D model: MSOP-10 (KiCad packages3D, STEP)
- 3D model files: `ad5174brmz-10-etched.step` / `ad5174brmz-10-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad5174brmz-10.step` / `ad5174brmz-10.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD5174.pdf) (20 pp, sha256 `9aad1c62688bcde2`, retrieved 2026-10-31, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ad5174brmz-10-datasheet.pdf)