AD5025BRUZ

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  "slug": "ad5025bruz",
  "title": "AD5025BRUZ",
  "brief": "Analog Devices Digital To Analog Converters (DACs), TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
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    "mpn": "AD5025BRUZ",
    "manufacturer": "Analog Devices",
    "package": "TSSOP-14",
    "pin_count": 14,
    "category": "ADC/DAC/Data Conversion",
    "subcategory": "Digital To Analog Converters (DACs)",
    "datasheet": "https://www.analog.com/media/en/technical-documentation/data-sheets/AD5025_5045_5065.pdf",
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      "lbr": "ad5025bruz.lbr"
    },
    "distributor_links": {
      "lcsc": "C649173",
      "digikey": "505-AD5025BRUZ-ND",
      "mouser": "584-AD5025BRUZ"
    },
    "distributor_check": {
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    },
    "pins": [
      {
        "number": "1",
        "name": "LDAC",
        "type": "input",
        "description": "Pulsing this pin low updates any or all DAC registers from pending input-register data, and it must be brought high after pulsing; it can be tied low only in standalone mode."
      },
      {
        "number": "2",
        "name": "SYNC",
        "type": "input",
        "description": "Active-low frame sync; data is clocked in on the falling edges of the next 32 SCLK clocks, and a SYNC rising edge before the 32nd falling edge aborts the write."
      },
      {
        "number": "3",
        "name": "VDD",
        "type": "power_in",
        "description": "Power supply input operating from 4.5 V to 5.5 V, to be decoupled with 10 µF in parallel with 0.1 µF to GND."
      },
      {
        "number": "4",
        "name": "VREFA",
        "type": "input",
        "description": "Reference voltage input for DAC A, with a reference input range of 2.2 V to VDD."
      },
      {
        "number": "5",
        "name": "VOUTA",
        "type": "output",
        "description": "Analog output voltage from DAC A, driven by a rail-to-rail output amplifier."
      },
      {
        "number": "6",
        "name": "POR",
        "type": "input",
        "description": "Power-on reset select: tying to GND powers up the output at 0 V and tying to VDD powers up at midscale."
      },
      {
        "number": "7",
        "name": "SDO",
        "type": "output",
        "description": "Serial data output for daisy-chaining or diagnostic read-back, changing on the SCLK rising edge and valid on the falling edge."
      },
      {
        "number": "8",
        "name": "CLR",
        "type": "input",
        "description": "Falling-edge-sensitive asynchronous clear that loads the programmed clear code (zero, midscale or full scale) into both DAC registers, with LDAC pulses ignored while low."
      },
      {
        "number": "9",
        "name": "VREFB",
        "type": "input",
        "description": "Reference voltage input for DAC B, with a reference input range of 2.2 V to VDD."
      },
      {
        "number": "10",
        "name": "VOUTB",
        "type": "output",
        "description": "Analog output voltage from DAC B, driven by a rail-to-rail output amplifier."
      },
      {
        "number": "11",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference point for all circuitry on the part."
      },
      {
        "number": "12",
        "name": "PDL",
        "type": "input",
        "description": "Power-down lockout: logic 0 prevents software power-down under any circumstance, and a high-to-low transition exits power-down to the previous DAC code when the part was previously powered down."
      },
      {
        "number": "13",
        "name": "DIN",
        "type": "input",
        "description": "Serial data input into a 32-bit shift register, clocked in on the falling edge of SCLK."
      },
      {
        "number": "14",
        "name": "SCLK",
        "type": "input",
        "description": "Serial clock input with data clocked on the falling edge, supporting rates up to 50 MHz."
      }
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        "guard_notes": [
          "extractor flagged: Pinout taken from Table 6 and Figure 5 (page 8), which covers the AD5025/AD5045/AD5065 family in the"
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        "at": "2026-10-28T16:03:57"
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      "Manufacturer": "Analog Devices",
      "Package": "TSSOP-14",
      "Category": "ADC/DAC/Data Conversion",
      "Pins": "14"
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