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AD5025BRUZ

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Analog Devices Digital To Analog Converters (DACs), TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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AD5025BRUZ

Analog Devices · Digital To Analog Converters (DACs) · TSSOP-14

AD5025BRUZ from Analog Devices, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 LDAC input Pulsing this pin low updates any or all DAC registers from pending input-register data, and it must be brought high after pulsing; it can be tied low only in standalone mode.
2 SYNC input Active-low frame sync; data is clocked in on the falling edges of the next 32 SCLK clocks, and a SYNC rising edge before the 32nd falling edge aborts the write.
3 VDD power_in Power supply input operating from 4.5 V to 5.5 V, to be decoupled with 10 µF in parallel with 0.1 µF to GND.
4 VREFA input Reference voltage input for DAC A, with a reference input range of 2.2 V to VDD.
5 VOUTA output Analog output voltage from DAC A, driven by a rail-to-rail output amplifier.
6 POR input Power-on reset select: tying to GND powers up the output at 0 V and tying to VDD powers up at midscale.
7 SDO output Serial data output for daisy-chaining or diagnostic read-back, changing on the SCLK rising edge and valid on the falling edge.
8 CLR input Falling-edge-sensitive asynchronous clear that loads the programmed clear code (zero, midscale or full scale) into both DAC registers, with LDAC pulses ignored while low.
9 VREFB input Reference voltage input for DAC B, with a reference input range of 2.2 V to VDD.
10 VOUTB output Analog output voltage from DAC B, driven by a rail-to-rail output amplifier.
11 GND power_in Ground reference point for all circuitry on the part.
12 PDL input Power-down lockout: logic 0 prevents software power-down under any circumstance, and a high-to-low transition exits power-down to the previous DAC code when the part was previously powered down.
13 DIN input Serial data input into a 32-bit shift register, clocked in on the falling edge of SCLK.
14 SCLK input Serial clock input with data clocked on the falling edge, supporting rates up to 50 MHz.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package TSSOP-14
Category ADC/DAC/Data Conversion
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Relative Accuracy (INL) TA -40C to +105C -0.25 0.25 LSB AD5025, TA = -40°C to +105°C 3
Relative Accuracy (INL) TA -40C to +125C -0.5 0.5 LSB AD5025, TA = -40°C to +125°C 3
Differential Nonlinearity DNL -1 0.2 1 LSB 3
Total Unadjusted Error TUE -2.5 0.2 2.5 mV VREF = 2.5 V; VDD = 5.5 V 3
Offset Error -1.8 0.2 1.8 mV Code 32 (AD5025) loaded to DAC register 3
Offset Error Drift -2 2 µV/°C 3
Full-Scale Error -0.07 0.01 0.07 % FSR All 1s loaded to DAC register, VREF < VDD 3
Gain Error -0.05 0.005 0.05 % FSR 3
Gain Temperature Coefficient -1 1 ppm of FSR/°C 3
DC Crosstalk due to full-scale output change 40 µV Single channel full-scale output change, RL = 5 kΩ to GND or VDD 3
DC Crosstalk due to load current change 40 µV/mA Due to load current change 3
DC Crosstalk due to powering down 40 µV Due to powering down (per channel) 3
Capacitive Load Stability CL 1 nF RL = 5 kΩ, RL = 100 kΩ, and RL = ∞ 3
DC Output Impedance Normal Mode 0.5 Ω Normal mode 3
Output Impedance Tolerance (100 kΩ network) -400 400 Ω Output connected to 100 kΩ network, power-down mode 3
Output Impedance Tolerance (1 kΩ network) -20 20 Ω Output connected to 1 kΩ network, power-down mode 3
Short-Circuit Current (full scale) 60 mA DAC = full scale, output shorted to GND 3
Short-Circuit Current (zero scale) 45 mA DAC = zero-scale, output shorted to VDD 3
Power-Up Time 4.5 µs Time to exit power-down mode to normal mode, 32nd clock edge to 90% of DAC midscale value, output unloaded 3
DC Power Supply Rejection Ratio PSRR -92 dB VDD ± 10%, DAC = full scale, VREF < VDD 3
Reference Input Range VREFIN 2.2 V Upper limit is VDD 3
Reference Current IREF 35 50 µA Per DAC channel 3
Reference Input Impedance 120 kΩ 3
Input Current IIN -1 1 µA Current flowing into or out of individual digital pins 4
Input Low Voltage VINL 0.8 V 4
Input High Voltage VINH 2.2 V 4
Pin Capacitance 4 pF 4
Output Low Voltage (SDO) VOL 0.4 V ISINK = 2 mA 4
High Impedance Leakage Current (SDO) -1 0.002 1 µA 4
High Impedance Output Capacitance 7 pF 4
Supply Voltage VDD VDD 4.5 5.5 V 4
Normal Mode Supply Current IDD 2.2 2.7 mA DAC active, excludes load current; VIH = VDD and VIL = GND 4
All Power-Down Modes Supply Current (TA -40C to +105C) IDD 0.4 2 µA TA = -40°C to +105°C 4
All Power-Down Modes Supply Current (TA -40C to +125C) IDD 30 µA TA = -40°C to +125°C 4
Output Voltage Settling Time (single-channel update) tS 5.8 8 µs ¼ to ¾ scale settling to ±1 LSB, RL = 5 kΩ, single-channel update including DAC calibration sequence 4
Output Voltage Settling Time (all-channel update) tS 10.7 13 µs ¼ to ¾ scale settling to ±1 LSB, RL = 5 kΩ, all channel update including DAC calibration sequence 4
Slew Rate SR 1.5 V/µs 4
Digital-to-Analog Glitch Impulse 4 nV-sec 1 LSB change around major carry 4
Multiplying Bandwidth BW 340 kHz VREF = 3 V ± 0.86 V p-p 4
Total Harmonic Distortion THD -80 dB VREF = 3 V ± 0.86 V p-p, frequency = 10 kHz 4
SCLK Cycle Time t1 20 ns Maximum SCLK frequency 50 MHz at VDD = 4.5 V to 5.5 V 5
SCLK High Time t2 10 ns 5
SCLK Low Time t3 10 ns 5
SYNC to SCLK Falling Edge Setup Time t4 16.5 ns 5
Data Setup Time t5 5 ns 5
Data Hold Time t6 5 ns 5
SCLK Falling Edge to SYNC Rising Edge t7 0 30 ns 5
Minimum SYNC High Time (Single Channel Update) t8 3 µs 5
Minimum SYNC High Time (All Channel Update) t8 8 µs 5
Absolute Maximum VDD to GND VDD -0.3 7 V 7
Absolute Maximum Digital Input Voltage to GND -0.3 V Upper limit VDD + 0.3 V 7
Absolute Maximum VOUTA or VOUTB to GND VOUT -0.3 V Upper limit VDD + 0.3 V 7
Absolute Maximum VREFA or VREFB to GND VREF -0.3 V Upper limit VDD + 0.3 V 7
Operating Temperature Range, Industrial TA -40 125 °C 7
Storage Temperature Range TSTG -65 150 °C 7
Junction Temperature (TJ MAX) TJ 150 °C 7
Thermal Impedance θJA 150.4 °C/W 7

CAD (KiCad official)

  • Symbol: AD5025BRUZ
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: ad5025bruz-etched.step / ad5025bruz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5025bruz.step / ad5025bruz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (25 pp, sha256 241f6ad70c0bd4a1, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF