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ACT8865QI405-T

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Qorvo DC-DC Converters, TQFN-32-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ACT8865QI405-T

Qorvo · DC-DC Converters · TQFN-32-EP(4x4)

ACT8865QI405-T from Qorvo, in a TQFN-32-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT1 input Output feedback sense for REG1; connect directly to the output node so the internal feedback network sets the output voltage.
2 GA power_in Analog ground; connect directly to a quiet ground node and tie GA, GP1, GP2 and GP3 together at a single point as close to the IC as possible.
3 OUT4 power_out REG4 LDO output, capable of up to 320mA; connect a 3.3µF ceramic capacitor from OUT4 to GA, and the output is discharged to GA through 1.5kΩ when disabled.
4 OUT5 power_out REG5 LDO output, capable of up to 320mA; connect a 3.3µF ceramic capacitor from OUT5 to GA, and the output is discharged to GA through 1.5kΩ when disabled.
5 INL45 power_in Power input for REG4 and REG5; bypass to GA with a high-quality ceramic capacitor placed as close to the IC as possible.
6 INL67 power_in Power input for REG6 and REG7; bypass to GA with a high-quality ceramic capacitor placed as close to the IC as possible.
7 OUT6 power_out REG6 LDO output, capable of up to 320mA; connect a 3.3µF ceramic capacitor from OUT6 to GA, and the output is discharged to GA through 1.5kΩ when disabled.
8 OUT7 power_out REG7 LDO output, capable of up to 320mA; connect a 3.3µF ceramic capacitor from OUT7 to GA, and the output is discharged to GA through 1.5kΩ when disabled.
9 nPBIN input Master enable input: drive through a 50kΩ resistor to GA to enable the IC, or drive directly to GA (low impedance, under 2.5kΩ) to assert manual reset; it is internally pulled up to VDDREF through 35kΩ.
10 PWRHLD input Power hold input; refer to the Control Sequences section for its function.
11 nRSTO output Active-low open-drain reset output that asserts on startup or manual reset and requires a 10kΩ or greater pull-up.
12 nIRQ output Open-drain interrupt output that asserts low when an unmasked fault or interrupt occurs and requires a 10kΩ or greater pull-up.
13 nPBSTAT output Active-low open-drain push-button status output that is asserted low whenever nPBIN is pushed and is high-Z otherwise.
14 GP3 power_in Power ground for REG3; connect together with GA, GP1 and GP2 at a single point as close to the IC as possible.
15 SW3 output Switching node output for REG3; connect to the switching end of the inductor.
16 VP3 power_in Power input for REG3; bypass to GP3 with a high-quality ceramic capacitor placed as close to the IC as possible.
17 PWREN input Power enable input; refer to the Control Sequences section for its function.
18 NC1 unconnected Not connected; not internally connected.
19 OUT3 input Output feedback sense for REG3; connect directly to the output node so the internal feedback network sets the output voltage.
20 VSEL input Step-down DC/DC output voltage selection: drive logic low to select the default output voltage and logic high to select the secondary output voltage.
21 SCL input Clock input for the I2C serial interface.
22 SDA bidirectional Data line for the I2C serial interface; data is read on the rising edge of SCL.
23 VDDREF power_in Power supply for the internal reference; connect directly to the system supply and bypass to GA with a 100nF capacitor placed as close to the IC as possible.
24 OUT2 input Output feedback sense for REG2; connect directly to the output node so the internal feedback network sets the output voltage.
25 NC2 unconnected Not connected; not internally connected.
26 VP2 power_in Power input for REG2 and system control; bypass to GP2 with a high-quality ceramic capacitor placed as close to the IC as possible.
27 SW2 output Switching node output for REG2; connect to the switching end of the inductor.
28 GP2 power_in Power ground for REG2; connect together with GA, GP1 and GP3 at a single point as close to the IC as possible.
29 GP1 power_in Power ground for REG1; connect together with GA, GP2 and GP3 at a single point as close to the IC as possible.
30 SW1 output Switching node output for REG1; connect to the switching end of the inductor.
31 VP1 power_in Power input for REG1; bypass to GP1 with a high-quality ceramic capacitor placed as close to the IC as possible.
32 REFBP passive Reference bypass; connect a 0.047µF ceramic capacitor from REFBP to GA, and it is discharged to GA in shutdown.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Qorvo
Package TQFN-32-EP(4x4)
Category Power Management (PMIC)
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VP1 to GP1, VP2 to GP2, VP3 to GP3 -0.3 6 V 7
INL, VDDREF to GA -0.3 6 V 7
nPBIN, SCL, SDA, REFBP, PWRHLD, PWREN, VSEL to GA -0.3 V 7
nRSTO, nIRQ, nPBSTAT to GA -0.3 6 V 7
SW1, OUT1 to GP1 -0.3 V 7
SW2, OUT2 to GP2 -0.3 V 7
SW3, OUT3 to GP3 -0.3 V 7
OUT4, OUT5, OUT6, OUT7 to GA -0.3 V 7
GP1, GP2, GP3 to GA -0.3 0.3 V 7
Operating Ambient Temperature -40 85 °C 7
Maximum Junction Temperature 125 °C 7
Storage Temperature -65 150 °C 7
Lead Temperature (Soldering, 10 sec) 300 °C Soldering, 10 sec 7
SCL, SDA Input Low 0.35 V VVDDREF = 3.1V to 5.5V, TA = -40ºC to 85ºC 8
SCL, SDA Input High 1.55 V VVDDREF = 3.1V to 5.5V, TA = -40ºC to 85ºC 8
SDA Output Low 0.35 V IOL = 5mA 8
SDA Leakage Current 1 µA 8
Input Voltage Range 2.7 5.5 V 14
UVLO Threshold Voltage 2.2 2.45 2.65 V VVDDREF Rising 14
Logic High Input Voltage 1.4 V 14
Logic Low Input Voltage 0.4 V 14
Leakage Current 1 µA VnIRQ = VnRSTO = 4.2V 14
Low Level Output Voltage 0.35 V ISINK = 5mA 14
Oscillator Frequency (System Control) 1.8 2 2.2 MHz 14
Shutdown Supply Current 1.5 3 µA All Regulators Disabled 14
Operating Voltage Range 2.7 5.5 V 15
UVLO Threshold Input Voltage Rising 2.5 2.6 2.7 V 15
Regulator Enabled (PWM Mode) 4.5 7 mA 15
Shutdown Current 0 1 µA VVP = 5.5V, Regulator Disabled 15
Output Voltage Accuracy (VOUT ≥ 1.2V, relative to VNOM) -1 1 % VOUT ≥ 1.2V, IOUT = 10mA 15
Output Voltage Accuracy (VOUT < 1.2V, relative to VNOM) -2 2 % VOUT < 1.2V, IOUT = 10mA 15
Oscillator Frequency (Step-Down) 1.8 2 2.2 MHz VOUT ≥ 20% of VNOM 15
REG1 Maximum Output Current 1.15 A 15
REG1 Current Limit 1.5 1.8 2.1 A 15
REG1 SW1 Leakage Current 1 µA VVP1 = 5.5V, VSW1 = 0 or 5.5V 15
REG2 Maximum Output Current 1.15 A 15
REG2 Current Limit 1.5 1.8 2.1 A 15
REG2 SW2 Leakage Current 1 µA VVP2 = 5.5V, VSW2 = 0 or 5.5V 15
REG3 Maximum Output Current 1.3 A 15
REG3 Current Limit 1.7 2.1 2.5 A 15
REG3 SW3 Leakage Current 0 1 µA VVP3 = 5.5V, VSW3 = 0 or 5.5V 15
Operating Voltage Range (LDO) 2.5 5.5 V 16
LDO Output Voltage Accuracy (VOUT ≥ 1.2V, relative to VNOM) -1 2 % VOUT ≥ 1.2V, TA = 25°C, IOUT = 10mA 16
LDO Output Voltage Accuracy (VOUT < 1.2V, relative to VNOM) -2 4 % VOUT < 1.2V, TA = 25°C, IOUT = 10mA 16
REG4 Dropout Voltage 90 180 mV IOUT = 160mA, VOUT > 3.1V 16
REG4 Maximum Output Current 320 mA 16
REG4 Current Limit 400 mA VOUT = 95% of regulation voltage 16
REG4 Stable COUT4 Range 3.3 20 µF 16
REG5 Dropout Voltage 140 280 mV IOUT = 160mA, VOUT > 3.1V 16
REG5 Maximum Output Current 320 mA 16
REG5 Current Limit 400 mA VOUT = 95% of regulation voltage 16
REG5 Stable COUT5 Range 3.3 20 µF 16
REG6 Dropout Voltage 90 180 mV IOUT = 160mA, VOUT > 3.1V 16
REG6 Maximum Output Current 320 mA 16
REG6 Current Limit 400 mA VOUT = 95% of regulation voltage 16
REG6 Stable COUT6 Range 3.3 20 µF 16
REG7 Dropout Voltage 140 280 mV IOUT = 160mA, VOUT > 3.1V 16
REG7 Maximum Output Current 320 mA 16
REG7 Current Limit 400 mA VOUT = 95% of regulation voltage 16
Junction to Ambient Thermal Resistance (θJA) θJA 27.5 °C/W 7

CAD (KiCad official)

  • Symbol: ACT8865QI405-T
  • Footprint: Package_DFN_QFN:QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm
  • 3D model: TQFN-32-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: act8865qi405-t-etched.step / act8865qi405-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); act8865qi405-t.step / act8865qi405-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Qorvo datasheet (31 pp, sha256 acdd6c9bcd6c6483, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF