ACSL-7210-00RE

{
  "slug": "acsl-7210-00re",
  "version": "0.1.0",
  "type": "component",
  "description": "Broadcom AVAGO Logic Output Optoisolators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "optoisolators",
    "acsl-7210-00re",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "acsl-7210-00re.kicad_sym",
    "acsl-7210-00re.kicad_mod",
    "acsl-7210-00re.glb",
    "acsl-7210-00re.step",
    "acsl-7210-00re.lbr",
    "docs/hero.png",
    "docs/acsl-7210-00re-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "acsl-7210-00re-hero.glb",
    "acsl-7210-00re-hero.overlay.json",
    "acsl-7210-00re-etched.glb"
  ],
  "component": {
    "mpn": "ACSL-7210-00RE",
    "manufacturer": "Broadcom AVAGO",
    "package": "SOIC-8",
    "pin_count": 8,
    "category": "Optoisolators",
    "subcategory": "Logic Output Optoisolators",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603058775586848768",
    "parts": {
      "symbol": "acsl-7210-00re.kicad_sym",
      "footprint": "acsl-7210-00re.kicad_mod",
      "model_3d": "acsl-7210-00re-hero.glb",
      "model_3d_plain": "acsl-7210-00re-etched.glb",
      "model_3d_step": "acsl-7210-00re-etched.step",
      "model_3d_step_plain": "acsl-7210-00re.step",
      "lbr": "acsl-7210-00re.lbr"
    },
    "distributor_links": {
      "lcsc": "C7466706",
      "mouser": "630-ACSL-7210-00RE"
    },
    "distributor_check": {
      "checked_at": "2026-10-19T08:38:34Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "error"
      },
      "mouser": {
        "pn": "630-ACSL-7210-00RE",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "VDD1",
        "type": "power_in",
        "description": "Side 1 supply, 3.0-3.6 V or 4.5-5.5 V recommended (6.5 V absolute max), with a 0.01-0.1 µF bypass capacitor placed close to VDD1 and GND1."
      },
      {
        "number": "2",
        "name": "VOA",
        "type": "output",
        "description": "Channel A CMOS output on the side 1, driven from VIA on pin 7, with VOH ≥ VDD - 0.1 V at -20 µA and VOL ≤ 0.1 V at 20 µA."
      },
      {
        "number": "3",
        "name": "VIB",
        "type": "input",
        "description": "Channel B CMOS logic input on side 1 that drives the LED, with VIH ≥ 0.7×VDD and VIL ≤ 0.3×VDD and input current of ±10 µA max."
      },
      {
        "number": "4",
        "name": "GND1",
        "type": "power_in",
        "description": "Ground for side 1, bypassed to VDD1 with a 0.01-0.1 µF capacitor."
      },
      {
        "number": "5",
        "name": "GND2",
        "type": "power_in",
        "description": "Ground for side 2, bypassed to VDD2 with a 0.01-0.1 µF capacitor."
      },
      {
        "number": "6",
        "name": "VOB",
        "type": "output",
        "description": "Channel B CMOS output on side 2, driven from VIB on pin 3, with VOH ≥ VDD - 0.1 V at -20 µA and VOL ≤ 0.1 V at 20 µA."
      },
      {
        "number": "7",
        "name": "VIA",
        "type": "input",
        "description": "Channel A CMOS logic input on side 2 that drives the LED, with VIH ≥ 0.7×VDD and VIL ≤ 0.3×VDD and input current of ±10 µA max."
      },
      {
        "number": "8",
        "name": "VDD2",
        "type": "power_in",
        "description": "Side 2 supply, 3.0-3.6 V or 4.5-5.5 V recommended (6.5 V absolute max), with a 0.01-0.1 µF bypass capacitor placed close to VDD2 and GND2."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The pin-to-signal mapping was reconstructed from the garbled text of the Functional Diagram (page 2); Supply and ground pin assignments (VDD1=1, GND1=4, GND2=5, VDD2=8) come from the functional diagram ; The functional diagram shows an internal 'Shield' node with no numbered package pin, so it is omitte"
        ],
        "pages_sent": 10,
        "cost_usd": 0.0615,
        "at": "2026-10-19T08:37:45"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603058775586848768",
        "pages": 10,
        "sha256": "bdd5079eded1bb79",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "acsl-7210-00re.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-10-19",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "acsl-7210-00re-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "78f92060ec516e0f171df18d23e17d388c483cfec249bff45d14f37db9b79cdd",
        "checked": "2026-10-19",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}