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ACSL-7210-00RE
Public Made by Adomby adom
Broadcom AVAGO Logic Output Optoisolators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownACSL-7210-00RE
Broadcom AVAGO · Logic Output Optoisolators · SOIC-8
ACSL-7210-00RE from Broadcom AVAGO, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Side 1 supply, 3.0-3.6 V or 4.5-5.5 V recommended (6.5 V absolute max), with a 0.01-0.1 µF bypass capacitor placed close to VDD1 and GND1. |
| 2 | VOA | output | Channel A CMOS output on the side 1, driven from VIA on pin 7, with VOH ≥ VDD - 0.1 V at -20 µA and VOL ≤ 0.1 V at 20 µA. |
| 3 | VIB | input | Channel B CMOS logic input on side 1 that drives the LED, with VIH ≥ 0.7×VDD and VIL ≤ 0.3×VDD and input current of ±10 µA max. |
| 4 | GND1 | power_in | Ground for side 1, bypassed to VDD1 with a 0.01-0.1 µF capacitor. |
| 5 | GND2 | power_in | Ground for side 2, bypassed to VDD2 with a 0.01-0.1 µF capacitor. |
| 6 | VOB | output | Channel B CMOS output on side 2, driven from VIB on pin 3, with VOH ≥ VDD - 0.1 V at -20 µA and VOL ≤ 0.1 V at 20 µA. |
| 7 | VIA | input | Channel A CMOS logic input on side 2 that drives the LED, with VIH ≥ 0.7×VDD and VIL ≤ 0.3×VDD and input current of ±10 µA max. |
| 8 | VDD2 | power_in | Side 2 supply, 3.0-3.6 V or 4.5-5.5 V recommended (6.5 V absolute max), with a 0.01-0.1 µF bypass capacitor placed close to VDD2 and GND2. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Broadcom AVAGO |
| Package | SOIC-8 |
| Category | Optoisolators |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Storage Temperature | TS | -55 | 125 | °C | 5 | ||
| Operating Temperature | TA | -40 | 105 | °C | 5 | ||
| Supply Voltage | VDD1, VDD2 | 0 | 6.5 | V | 5 | ||
| Input Voltage | VIA, VIB | -0.5 | V | 5 | |||
| Output Voltage | VOA, VOB | -0.5 | V | 5 | |||
| Average Output Current | IO | 10 | mA | 5 | |||
| Input Power Dissipation | PI | 72 | mW | Per channel | 5 | ||
| Output Power Dissipation | PO | 62 | mW | Per channel | 5 | ||
| Lead Solder Temperature | TLS | 260 | °C | for 10 s, 1.6 mm below seating plane | 5 | ||
| Operating Temperature | TA | -40 | 105 | °C | 5 | ||
| Supply Voltage (3.3V) | VDD1, VDD2 | 3 | 3.6 | V | 5 | ||
| Supply Voltage (5V) | VDD1, VDD2 | 4.5 | 5.5 | V | 5 | ||
| Logic Low Input Voltage | VIL | 0 | V | 5 | |||
| Input Signal Rise and Fall Times | tr, tf | 1 | ms | 5 | |||
| Logic Low Supply Current | IDD1L, IDD2L | 9 | 15 | mA | VI = 0V, Figure 1 | 5 | |
| Logic High Supply Current | IDD1H, IDD2H | 1.9 | 5 | mA | VI = VDD, Figure 2 | 5 | |
| Input Current | IIA, IIB | -10 | 10 | µA | 5 | ||
| Logic Low Output Voltage | VOL | 0 | 0.1 | V | IO = 20 μA, VI = VIL | 5 | |
| Logic Low Output Voltage | VOL | 0.14 | 1 | V | IO = 4 mA, VI = VIL | 5 | |
| Propagation Delay Time to Logic Low Output | tPHL | 27 | 40 | ns | CL= 15 pF, CMOS Signal Levels, Figure 3, Figure 4 | 6 | |
| Propagation Delay Time to Logic High Output | tPLH | 25 | 40 | ns | CL= 15 pF, CMOS Signal Levels, Figure 3, Figure 4 | 6 | |
| Pulse Width | tPW | 40 | ns | CL= 15 pF, CMOS Signal Levels | 6 | ||
| Pulse Width Distortion | /tPHL, tPLH/ | 1.8 | 8 | ns | 3V ≤ VDD ≤ 3.6V, CL= 15 pF, CMOS Signal Levels, Figure 5, Figure 6 | 6 | |
| Pulse Width Distortion | /tPHL, tPLH/ | 10 | ns | CL= 15 pF, CMOS Signal Levels | 6 | ||
| Propagation Delay Skew | tPSK | 20 | ns | CL= 15 pF, CMOS Signal Levels | 6 | ||
| Common Mode Transient Immunity at Logic High Output | /CMH/ | 25 | 35 | kV/µs | VCM = 1000V, TA = 25 °C, VI = VDD1, VO > 0.8 × VDD2 | 6 | |
| Common Mode Transient Immunity at Logic Low Output | /CML/ | 25 | 35 | kV/µs | VCM = 1000V, TA = 25°C, VI = 0V, VO < 0.8V | 6 | |
| Input-Output Insulation | VISO | 3750 | VRMS | RH < 50% for 1 min., TA = 25°C | 6 |
CAD (KiCad official)
- Symbol:
ACSL-7210-00RE - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
acsl-7210-00re-etched.step/acsl-7210-00re-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);acsl-7210-00re.step/acsl-7210-00re.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Broadcom AVAGO datasheet (10 pp, sha256
bdd5079eded1bb79, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).