ACPL-C870-500E

{
  "slug": "acpl-c870-500e",
  "version": "0.1.0",
  "type": "component",
  "description": "AVAGO(Broadcom) Isolation Amplifiers, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "operational amplifier-comparator",
    "acpl-c870-500e",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
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    "path": "docs/hero.png"
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  "files": [
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    "README.md",
    "acpl-c870-500e.kicad_sym",
    "acpl-c870-500e.kicad_mod",
    "acpl-c870-500e.glb",
    "acpl-c870-500e.step",
    "acpl-c870-500e.lbr",
    "docs/hero.png",
    "docs/acpl-c870-500e-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "acpl-c870-500e-hero.glb",
    "acpl-c870-500e-hero.overlay.json",
    "acpl-c870-500e-etched.glb"
  ],
  "component": {
    "mpn": "ACPL-C870-500E",
    "manufacturer": "AVAGO(Broadcom)",
    "package": "SO-8",
    "pin_count": 8,
    "category": "Operational Amplifier/Comparator",
    "subcategory": "Isolation Amplifiers",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589839550202871808",
    "parts": {
      "symbol": "acpl-c870-500e.kicad_sym",
      "footprint": "acpl-c870-500e.kicad_mod",
      "model_3d": "acpl-c870-500e-hero.glb",
      "model_3d_plain": "acpl-c870-500e-etched.glb",
      "model_3d_step": "acpl-c870-500e-etched.step",
      "model_3d_step_plain": "acpl-c870-500e.step",
      "lbr": "acpl-c870-500e.lbr"
    },
    "distributor_links": {
      "lcsc": "C2057423"
    },
    "distributor_check": {
      "checked_at": "2026-10-18T18:54:00Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "quota"
      },
      "mouser": {
        "pn": null,
        "status": "quota"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "VDD1",
        "type": "power_in",
        "description": "Supply voltage for the input side, 4.5 V to 5.5 V relative to GND1, with a 0.1 µF bypass capacitor required between pins 1 and 4."
      },
      {
        "number": "2",
        "name": "VIN",
        "type": "power_in",
        "description": "Voltage input with a 0 to 2.0 V recommended range referenced to GND1 (2 V nominal, 2.46 V full-scale), and a steady-state absolute range of −2 V to VDD1 + 0.5 V."
      },
      {
        "number": "3",
        "name": "SHDN",
        "type": "input",
        "description": "Active-high shutdown pin; the shutdown enable voltage is VDD1 − 0.5 V to VDD1 V, and shutdown reduces IDD1 to about 15 µA."
      },
      {
        "number": "4",
        "name": "GND1",
        "type": "power_in",
        "description": "Input-side ground reference for VDD1, VIN and SHDN, paired with the 0.1 µF bypass capacitor to pin 1."
      },
      {
        "number": "5",
        "name": "GND2",
        "type": "power_in",
        "description": "Output-side ground reference for VDD2 and the differential outputs, paired with the 0.1 µF bypass capacitor to pin 8."
      },
      {
        "number": "6",
        "name": "VOUT-",
        "type": "output",
        "description": "Negative differential output with an output common-mode voltage of 1.23 V typical and absolute range of −0.5 V to VDD2 + 0.5 V."
      },
      {
        "number": "7",
        "name": "VOUT+",
        "type": "output",
        "description": "Positive differential output with an output common-mode voltage of 1.23 V typical and absolute range of −0.5 V to VDD2 + 0.5 V."
      },
      {
        "number": "8",
        "name": "VDD2",
        "type": "power_in",
        "description": "Supply voltage for the output side, 3 V to 5.5 V referenced to GND2, with a 0.1 µF bypass capacitor required between pins 5 and 8."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The package hint says SO-8, but the datasheet describes this part as a Stretched SO-8 (SSO-8) packag; Table 2 (Ordering Information) lists ACPL-C870 under the -500E option as Surface Mount, Tape and Ree; The datasheet gives one pinout for the whole family and does not list a separate pinout per option, ",
          "1/8 pins cited to the wrong page (name found elsewhere): ['3:SHDN@p5']"
        ],
        "pages_sent": 16,
        "cost_usd": 0.0665,
        "at": "2026-10-18T18:53:44"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589839550202871808",
        "pages": 16,
        "sha256": "9828a505b30e5f86",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
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      "footprint": "viewers/footprint.html"
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        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "acpl-c870-500e-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
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        "sha256": "8dee8a338ab9a138e22c2a5fdcafdca13588a0fa62fcc1517f7f9b12f2782784",
        "checked": "2026-10-18",
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  }
}