component
ACPL-C870-500E
Public Made by Adomby adom
AVAGO(Broadcom) Isolation Amplifiers, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownACPL-C870-500E
AVAGO(Broadcom) · Isolation Amplifiers · SO-8
ACPL-C870-500E from AVAGO(Broadcom), in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Supply voltage for the input side, 4.5 V to 5.5 V relative to GND1, with a 0.1 µF bypass capacitor required between pins 1 and 4. |
| 2 | VIN | power_in | Voltage input with a 0 to 2.0 V recommended range referenced to GND1 (2 V nominal, 2.46 V full-scale), and a steady-state absolute range of −2 V to VDD1 + 0.5 V. |
| 3 | SHDN | input | Active-high shutdown pin; the shutdown enable voltage is VDD1 − 0.5 V to VDD1 V, and shutdown reduces IDD1 to about 15 µA. |
| 4 | GND1 | power_in | Input-side ground reference for VDD1, VIN and SHDN, paired with the 0.1 µF bypass capacitor to pin 1. |
| 5 | GND2 | power_in | Output-side ground reference for VDD2 and the differential outputs, paired with the 0.1 µF bypass capacitor to pin 8. |
| 6 | VOUT- | output | Negative differential output with an output common-mode voltage of 1.23 V typical and absolute range of −0.5 V to VDD2 + 0.5 V. |
| 7 | VOUT+ | output | Positive differential output with an output common-mode voltage of 1.23 V typical and absolute range of −0.5 V to VDD2 + 0.5 V. |
| 8 | VDD2 | power_in | Supply voltage for the output side, 3 V to 5.5 V referenced to GND2, with a 0.1 µF bypass capacitor required between pins 5 and 8. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | AVAGO(Broadcom) |
| Package | SO-8 |
| Category | Operational Amplifier/Comparator |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Offset Voltage | VOS | -9.9 | -0.3 | 9.9 | mV | TA = 25°C | 6 |
| Gain (ACPL-C870, ±3%) | G3 | 0.97 | 1 | 1.03 | V/V | TA = 25°C | 6 |
| Nonlinearity | NL | 0.05 | 0.1 | % | VIN = 0 to 2V, TA = 25°C | 6 | |
| Input Bias Current | IIN | -0.1 | -0.0015 | µA | VIN = 0 V | 6 | |
| Small-Signal Bandwidth (-3 dB) | f-3dB | 70 | 100 | kHz | Guaranteed by design | 6 | |
| Input to Output Propagation Delay, 50% to 10% | tPD10 | 2.2 | 3 | µs | Step input | 6 | |
| Input to Output Propagation Delay, 50% to 50% | tPD50 | 3.7 | 5.5 | µs | Step input | 6 | |
| Input to Output Propagation Delay, 50% to 90% | tPD90 | 5.3 | 6.5 | µs | Step input | 6 | |
| Output Rise/Fall Time (10% to 90%) | tR/F | 2.7 | 4 | µs | Step input (tPD90, tPD10) | 7 | |
| Shutdown Delay | tSD | 25 | 40 | µs | Vin = 2V | 7 | |
| Enable Delay | tON | 150 | 200 | µs | 7 | ||
| Common Mode Transient Immunity | CMTI | 10 | 15 | kV/µs | VCM = 1 kV, TA = 25°C | 7 | |
| Input Side Supply Current (VSD = 0V) | IDD1 | 10.5 | 15 | mA | VSD = 0V | 7 | |
| Output Side Supply Current (5V supply) | IDD2 | 6.5 | 12 | mA | 5V supply | 7 | |
| Output Side Supply Current (3.3V supply) | IDD2 | 6.1 | 11 | mA | 3.3V supply | 7 | |
| Input-Output Momentary Withstand Voltage | VISO | 5000 | Vrms | RH < 50%, t = 1 min., TA = 25°C | 7 | ||
| Storage Temperature | TS | -55 | 125 | °C | 5 | ||
| Ambient Operating Temperature (absolute maximum) | TA | -40 | 105 | °C | 5 | ||
| Supply Voltage | VDD1, VDD2 | -0.5 | 6 | V | 5 | ||
| Steady-State Input Voltage | VIN | -2 | V | 5 | |||
| Two-Second Transient Input Voltage | VIN | -6 | V | 5 | |||
| Logic Input Voltage | VSD | -0.5 | V | 5 | |||
| Output Voltages | VOUT+, VOUT- | -0.5 | V | 5 | |||
| Ambient Operating Temperature (recommended) | TA | -40 | 105 | °C | 5 | ||
| VDD1 Supply Voltage | VDD1 | 4.5 | 5.5 | V | 5 | ||
| VDD2 Supply Voltage | VDD2 | 3 | 5.5 | V | 5 | ||
| Input Voltage Range | VIN | 0 | 2 | V | 5 |
CAD (KiCad official)
- Symbol:
ACPL-C870-500E - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files:
acpl-c870-500e-etched.step/acpl-c870-500e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);acpl-c870-500e.step/acpl-c870-500e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: AVAGO(Broadcom) datasheet (16 pp, sha256
9828a505b30e5f86, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).