ACPL-061L-500E

{
  "slug": "acpl-061l-500e",
  "version": "0.1.0",
  "type": "component",
  "description": "Broadcom AVAGO Logic Output Optoisolators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
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    "optoisolators",
    "acpl-061l-500e",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "acpl-061l-500e.kicad_sym",
    "acpl-061l-500e.kicad_mod",
    "acpl-061l-500e.glb",
    "acpl-061l-500e.step",
    "acpl-061l-500e.lbr",
    "docs/hero.png",
    "docs/acpl-061l-500e-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "acpl-061l-500e-hero.glb",
    "acpl-061l-500e-hero.overlay.json",
    "acpl-061l-500e-etched.glb"
  ],
  "component": {
    "mpn": "ACPL-061L-500E",
    "manufacturer": "Broadcom AVAGO",
    "package": "SOIC-8",
    "pin_count": 8,
    "category": "Optoisolators",
    "subcategory": "Logic Output Optoisolators",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590225955916066816",
    "parts": {
      "symbol": "acpl-061l-500e.kicad_sym",
      "footprint": "acpl-061l-500e.kicad_mod",
      "model_3d": "acpl-061l-500e-hero.glb",
      "model_3d_plain": "acpl-061l-500e-etched.glb",
      "model_3d_step": "acpl-061l-500e-etched.step",
      "model_3d_step_plain": "acpl-061l-500e.step",
      "lbr": "acpl-061l-500e.lbr"
    },
    "distributor_links": {
      "lcsc": "C2985493"
    },
    "distributor_check": {
      "checked_at": "2026-10-18T15:00:39Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "quota"
      },
      "mouser": {
        "pn": null,
        "status": "quota"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "NC",
        "type": "unconnected",
        "description": "Not connected on the ACPL-061L SO-8 package."
      },
      {
        "number": "2",
        "name": "Anode",
        "type": "input",
        "description": "LED anode input; the datasheet specifies an input forward current of 1.6 mA to 6.0 mA (IFH) with a 8 mA maximum average forward input current."
      },
      {
        "number": "3",
        "name": "Cathode",
        "type": "input",
        "description": "LED cathode input; the datasheet specifies a maximum average forward input current of 8 mA and a reverse input voltage of 5 V maximum."
      },
      {
        "number": "4",
        "name": "NC",
        "type": "unconnected",
        "description": "Not connected on the ACPL-061L SO-8 package."
      },
      {
        "number": "5",
        "name": "GND",
        "type": "power_in",
        "description": "Output-side ground; a 0.1 µF bypass capacitor must be connected between VDD and GND, with total lead length not exceeding 20 mm."
      },
      {
        "number": "6",
        "name": "Vo",
        "type": "output",
        "description": "Push-pull CMOS output with slew-rate control; output voltage is limited to -0.5 V to VDD + 0.5 V and output current to 10 mA maximum."
      },
      {
        "number": "7",
        "name": "NC",
        "type": "unconnected",
        "description": "Not connected on the ACPL-061L (footnote states pin 7 is not connected)."
      },
      {
        "number": "8",
        "name": "VDD",
        "type": "power_in",
        "description": "Output-side supply; the recommended supply range is 2.7 V to 5.5 V with a 6.5 V absolute maximum, and a 0.1 µF bypass capacitor is required between VDD and GND."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The page 1 pin diagram text is garbled in extraction. Pin 7 NC is confirmed by the footnote ('Pin 7 ; VDD on pin 8 is inferred from the garbled diagram. The footnote rules out pin 7, and VDD is the only; The SHIELD shown in the ACPL-061L diagram is an internal Faraday shield, not a numbered package pin,"
        ],
        "pages_sent": 17,
        "cost_usd": 0.0949,
        "at": "2026-10-18T14:58:49"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590225955916066816",
        "pages": 17,
        "sha256": "a7df20103dbe2929",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
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        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
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        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "acpl-061l-500e-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
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          1.75
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        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "41af7b3e7431cc318dbefa717eb18c21cb511d642508374056d45a5ea942fa28",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}