A89500GEJTR-T from Allegro MicroSystems, LLC, in a DFN-10(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VCC	power_in	Gate drive power supply input, 8 to 15 V operating range, to be decoupled with a ceramic capacitor CVCC close to the VCC and GND terminals.
2	NC	unconnected	No internal connection; connect to GND.
3	C	passive	Bootstrap capacitor connection (positive supply for the high-side gate driver), with CBOOT connected between C and S.
4	GH	output	High-side gate drive output for an external N-channel MOSFET.
5	S	passive	Load connection and source reference of the high-side MOSFET, negative supply reference for the floating high-side driver.
6	RESETn	input	Active-low standby mode control logic input that puts the device into low-power sleep mode when taken low, with 50 kΩ typical pull-down.
7	HS	input	High-side control logic input, active high, 3.3 V and 5 V compatible with 50 kΩ typical pull-down.
8	LS	input	Low-side control logic input, active high, 3.3 V and 5 V compatible with 50 kΩ typical pull-down.
9	GND	power_in	Analog, digital, and power ground; connect to supply ground.
10	GL	output	Low-side gate drive output for an external N-channel MOSFET, referenced to GND.
11	PAD	power_in	Exposed thermal pad; connect to GND.

Key specifications

Parameter	Value
Manufacturer	Allegro MicroSystems, LLC
Package	DFN-10(3x3)
Category	Power Supply Chip
Pins	11

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
VCC Functional Operating Range, outputs active	VCC	8		15	V	Operating, outputs active	5
VCC Functional Operating Range, no unsafe states	VCC	0		15	V	No unsafe states	5
VCC Quiescent Current	ICCQ			3	mA	RESETn = high, all gate drive outputs low	5
VCC Sleep Current	ICCS			20	µA	RESETn ≤ 300 mV, sleep mode	5
VCC Undervoltage	VCCUV	6.3	6.65	7	V	VCC falling	5
VCC Undervoltage Hysteresis	VCCUVHys	0.2		0.5	V		5
Internal Logic Supply Regulator Voltage	VDL	3	3.3	3.6	V		5
Bootstrap Diode Forward Voltage	VfBOOT	0.7	1.3	1.7	V	ID = 1 mA	5
Bootstrap Diode Forward Voltage	VfBOOT	1.6	2	2.4	V	ID = 100 mA	5
Turn-On Time, High-Side	tr(HS)		105	231	ns	CLOAD = 33 nF, 2 to 8 V, VC, VS = 12 V	5
Turn-On Time, Low-Side	tr(LS)		105	231	ns	CLOAD = 33 nF, 2 to 8 V, VCC = 12 V	5
Turn-Off Time, High-Side	tf(HS)		46	133	ns	CLOAD = 33 nF, 8 to 2 V, VC, VS = 12 V	5
Turn-Off Time, Low-Side	tf(LS)		46	133	ns	CLOAD = 33 nF, 8 to 2 V, VCC = 12 V	5
Pull-Up Peak Source Current, High-Side	IPUPK(HS)		-2.7	-1.5	A	VC, VS = 12 V	5
Pull-Up Peak Source Current, Low-Side	IPUPK(LS)		-2.7	-1.5	A	VCC = 12 V	5
Pull-Up On Resistance	RDS(on)UP	1.2		3.4	Ω	TJ = 25°C, IGH = -150 mA	5
Pull-Down Peak Sink Current	IPDPK	3.1	5.2		A	VCC = 12 V	5
Pull-Down On Resistance	RDS(on)DN	0.4		1	Ω	TJ = 25°C, IGL = -150 mA	5
GL Output Voltage Low	VGLL			0.02	V	-1 mA < IGL, 1 mA	5
GH Passive Pull-Down	RGHPD	45	950	1700	kΩ	VCC open circuit, VGH, VS = 0.1 V	5
GL Passive Pull-Down	RGLPD	45	950	1700	kΩ	VCC open circuit, VGL = 0.1 V	5
GH Active Pull-Down	RGHPA	5.9	10	37.6	kΩ	VC, VS > 3 V	5
GL Active Pull-Down	RGLPA	5.9	10	37.6	kΩ	VCC > 3 V	5
Turn-Off Propagation Delay	tP(off)	17		32	ns	Input change to unloaded gate output change	5
Turn-On Propagation Delay	tP(on)	17		32	ns	Input change to unloaded gate output change	5
Propagation Delay Matching (On to Off)	ΔtOO		3	15	ns		5
Input Low Voltage	VIL			1	V	HS, LS, RESETn	5
Input High Voltage	VIH	2			V	HS, LS, RESETn	5
Input Hysteresis	VIhys	200	300	600	mV	All logic inputs	5
Input Pull-Down	RPD		50		kΩ	LS, HS, RESETn, 0 < VIN < 6 V	5
Supply Voltage	VCC	-0.3		18	V	VCC, with respect to GND	2
Logic Input Terminals	VIB	-0.3		6	V	HS, LS, RESETn	2
Low-Side Gate Drive Output Terminal	VGL	-0.3		18	V	GL	2
Ambient Operating Temperature Range	TA	-40		105	°C	Range G, limited by power dissipation	2
Maximum Continuous Junction Temperature	TJ(max)			165	°C		2
Transient Junction Temperature	TJt			180	°C	Overtemperature event not exceeding 10 seconds; lifetime duration not exceeding 10 hours; guaranteed by design characterization	2
Storage Temperature Range	Tstg	-55		150	°C		2
Package Thermal Resistance	RθJA		28		°C/W	4-layer PCB based on JEDEC standard	2
Package Thermal Resistance	RθJA		38		°C/W	2-layer PCB with 3.8 in.2 copper each side	2
Package Thermal Resistance, junction to pad	RθJP		2		°C/W		2

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts		tin	wettable flank and exposed thermal pad. This package is lead (Pb) free, with 100% matte-tin leadframe plating.	1

CAD (KiCad official)

Symbol: A89500GEJTR-T
Footprint: Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm
3D model: DFN-10(3x3) (KiCad packages3D, STEP)
3D model files: a89500gejtr-t-etched.step / a89500gejtr-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); a89500gejtr-t.step / a89500gejtr-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Allegro MicroSystems, LLC datasheet (13 pp, sha256 0d8c9a6705f8449e, retrieved 2026-10-30, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

A89500GEJTR-T

Verified A89500GEJTR-T

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3D Model

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