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A4963GLPTR-T

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Allegro MicroSystems, LLC Motor Driver ICs, TSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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A4963GLPTR-T

Allegro MicroSystems, LLC · Motor Driver ICs · TSSOP-20-EP

A4963GLPTR-T from Allegro MicroSystems, LLC, in a TSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBB power_in Main supply for internal regulators and charge pump, 4.2 to 50 V operating (absolute max 50 V), connected through reverse-voltage protection and decoupled with ceramic capacitors.
2 FAULTn output Open-drain active-low fault output that can be tied to the PWM input for a single-wire ECU interface and can be shorted to ground or VBB without damage (-0.3 to 50 V).
3 SPD output Open-drain speed output with programmable FG (electrical cycle) or TACHO (commutation) frequency, can be shorted to ground or VBB without damage (-0.3 to 50 V).
4 PWM input Programmable PWM input setting the motor operating mode and proportional duty-cycle demand, pulled low for fault, -0.3 to 50 V and can be shorted to ground or VBB without damage.
5 SDO tri_state Serial data output that is high impedance when STRn is high and outputs the diagnostic register fault flag (bit 15) as soon as STRn goes low (-0.3 to 6.5 V).
6 SCK input Serial clock that latches SDI on the rising edge, requires 16 rising edges per write and must be held high when STRn changes (-0.3 to 6.5 V).
7 STRn input Serial strobe (chip select) input, active low; when high, SCK and SDI activity is ignored and SDO is high impedance (-0.3 to 6.5 V).
8 SDI input Serial data input, 16-bit word MSB first (-0.3 to 6.5 V).
9 GND power_in Analog reference, digital and power ground, connected to supply ground.
10 CSM input Negative differential current sense amplifier input, connected directly to one end of the sense resistor with a separate PCB trace (-4 to 6.5 V).
11 CSP input Positive differential current sense amplifier input, connected directly to one end of the sense resistor with a separate PCB trace (-4 to 6.5 V).
12 GLC output Phase C low-side gate drive output for the external N-channel MOSFET (-0.3 to 18 V).
13 GLB output Phase B low-side gate drive output for the external N-channel MOSFET (-0.3 to 18 V).
14 GLA output Phase A low-side gate drive output for the external N-channel MOSFET (-0.3 to 18 V).
15 GHC output Phase C high-side gate drive output for the external P-channel MOSFET (VBB - 18 to VBB + 0.3 V).
16 GHB output Phase B high-side gate drive output for the external P-channel MOSFET (VBB - 18 to VBB + 0.3 V).
17 GHA output Phase A high-side gate drive output for the external P-channel MOSFET (VBB - 18 to VBB + 0.3 V).
18 SC input Phase C motor connection that senses the voltage switched across the load (-4 to 51 V).
19 SB input Phase B motor connection that senses the voltage switched across the load (-4 to 51 V).
20 SA input Phase A motor connection that senses the voltage switched across the load (-4 to 51 V).
21 PAD passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Allegro MicroSystems, LLC
Package TSSOP-20-EP
Category Power Supply Chip
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VBB Functional Operating Range (outputs active) VBB 4.2 50 V Operating; outputs active 6
VBB Functional Operating Range (outputs disabled) VBB 4 50 V Operating; outputs disabled 6
VBB Functional Operating Range (no unsafe states) VBB 0 50 V No unsafe states 6
VBB Quiescent Current IBBQ 12 18 mA PWM = inactive, VBB = 12 V 6
System Clock Period tOSC 47.5 50 52.5 ns 6
GHx Pull-Up On Resistance RGHUP 12 17 26 Ω TJ = 25°C, IGHx = -40 mA 6
GHx Pull-Down On Resistance RGHDN 23 28 33 Ω TJ = 25°C, IGHx = 40 mA, VBB = 10 V 6
GHx Output Voltage High (Off) VGHH -0.2 V -10 µA < IGH < 10 µA (printed VBB, 0.2 min) 6
GHx Output Voltage Low (Active) VGHL 0.9 2.6 V IGH = 10 mA, VBB = 14.5 V 6
GLx Pull-Up On Resistance RGLUP 17 24 31 Ω TJ = 25°C, IGLx = -40 mA, VBB = 10 V 6
GLx Pull-Down On Resistance RGLDN 15 20 25 Ω TJ = 25°C, IGLx = 40 mA 6
GLx Pull-Down On Resistance (150°C) RGLDN 30 40 50 Ω TJ = 150°C, IGLx = 40 mA 6
GLx Output Voltage High (Active) VGLH 10.7 13.5 V IGL = -10 mA, VBB = 14.5 V 6
GLx Output Voltage Low (Off) VGLL 0.2 V -10 µA < IGL < 10 µA 6
Turn-Off Propagation Delay tP(off) 200 250 400 ns Input change to unloaded gate output change; Direct mode 6
Turn-On Propagation Delay tP(on) 200 250 400 ns Input change to unloaded gate output change; Direct mode 6
Dead Time tDEAD 0.9 1 1.1 µs Default power-up value 6
Input Low Voltage VIL 0.8 V 7
Input High Voltage VIH 2 V 7
Input Hysteresis VIhys 150 550 mV 7
Input Pull-Down Resistor (PWM, SDI, SCK) RPD 30 50 70 kΩ 7
Input Pull-Up Resistor (STRn) RPU 30 50 70 kΩ 7
Output Low Voltage (SDO) VOL 0.2 0.4 V IOL = 1 mA 7
Output High Voltage (SDO) VOH 2.4 3 V IOL = 1 mA 7
Output Leakage (SDO) IO -1 1 µA 0 V < VO < 3.3 V, STRn = 1 7
Output Low Voltage (FAULTn, SPD) VOL 0.2 0.4 V IOL = 4 mA, FAULTn active 7
Output Current Limit (FAULTn, SPD) IOLIM 10 15 mA 0 V < VO < 15 V, FAULTn active 7
Output Current Limit (FAULTn, SPD) high voltage IOLIM 2 mA 15 V ≤ VO < 50 V, FAULTn active 7
Output Leakage (FAULTn, SPD) IO -1 1 µA 0 V < VO < 12 V, FAULTn inactive 7
Output Leakage (FAULTn, SPD) high voltage IO 1.7 mA 12 V ≤ VO < 50 V, FAULTn inactive 7
PWM Duty Detect Frequency Range fPWD 5 1000 Hz 7
PWM Brake Time tBRK 500 µs 7
Clock High Time tSCKH 50 ns A in Figure 1 7
Clock Low Time tSCKL 50 ns B in Figure 1 7
Strobe Lead Time tSTLD 30 ns C in Figure 1 7
Strobe Lag Time tSTLG 30 ns D in Figure 1 7
Strobe High Time tSTRH 300 ns E in Figure 1 7
Data Out Enable Time tSDOE 40 ns F in Figure 1 7
Data Out Disable Time tSDOD 30 ns G in Figure 1 7
Data Out Valid Time from Clock Falling tSDOV 40 ns H in Figure 1 7
Data Out Hold Time from Clock Falling tSDOH 5 ns I in Figure 1 7
Data In Setup Time to Clock Rising tSDIS 15 ns J in Figure 1 7
Data In Hold Time from Clock Rising tSDIH 10 ns K in Figure 1 7
Hold Duty Cycle DH 35.5 37.5 39.5 % Default power-up value 7
Hold Time tHOLD 15.2 16 16.8 ms Default power-up value 7
Start Speed fST 7.6 8 8.4 Hz Default power-up value 7
Start Duty Cycle DST 47.5 50 52.5 % Default power-up value 7
Phase Advance θADV 14 15 16 ° Default power-up value 8
Maximum Control Speed fMX 3112.9 3276.7 3440.5 Hz Default power-up value 8
Speed Error EfCCMX -5 5 % 8
Current Limit Threshold Voltage Range VILIM 12.5 200 mV VILIM = VCSP, VCSM 8
Current Limit Threshold Voltage Error EILIM -5 5 %FS VILIM = 200 mV 8
Fixed Off-Time tPW 47.9 50.4 52.9 µs Default power-up value 8
Blank Time tBL 3.04 3.2 3.36 µs Default power-up value 8
VBB Undervoltage Lockout (rising) VBBON 4.2 4.4 4.6 V VBB rising 8
VBB Undervoltage Lockout (falling) VBBOFF 3.8 4 4.2 V VBB falling 8
VBB POR Voltage VBBR 3.2 3.5 V VBB falling 8
VDS Threshold VDST 1325 1550 1705 mV Default power-up value 8
Temperature Warning Threshold TJWH 125 135 145 °C Temperature increasing 8
Overtemperature Threshold TJF 170 175 180 °C Temperature increasing 8
Supply Voltage VBB -0.3 50 V With respect to GND 3
Ambient Operating Temperature Range TA -25 150 °C 3
Maximum Continuous Junction Temperature TJ(max) 165 °C 3
Storage Temperature Range Tstg -55 150 °C 3
Package Thermal Resistance RθJA 44 °C/W 2-layer PCB with 3 in.2 copper each side 3
Package Thermal Resistance junction to thermal pad RθJT 2 °C/W 3

CAD (KiCad official)

  • Symbol: A4963GLPTR-T
  • Footprint: Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm
  • 3D model: TSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: a4963glptr-t-etched.step / a4963glptr-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); a4963glptr-t.step / a4963glptr-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Allegro MicroSystems, LLC datasheet (42 pp, sha256 88b25f3118cd7ef6, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF