component
A4953ELJTR-T
Public Made by Adomby adom
Allegro MicroSystems, LLC Motor Driver ICs, SOIC-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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A4953ELJTR-T
Allegro MicroSystems, LLC · Motor Driver ICs · SOIC-8-EP
A4953ELJTR-T from Allegro MicroSystems, LLC, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground; a star ground should be located as close to the device as possible. |
| 2 | IN2 | input | Logic input 2 for bridge control (VIN(1) min 2.0 V, VIN(0) max 0.8 V, 50 kΩ typ internal pull-down); both inputs low for over 1 ms enters Low Power Standby mode. |
| 3 | IN1 | input | Logic input 1 for bridge control (VIN(1) min 2.0 V, VIN(0) max 0.8 V, 50 kΩ typ internal pull-down); both inputs low for over 1 ms enters Low Power Standby mode. |
| 4 | VREF | power_in | Analog input setting the PWM current limit, 0 to 5 V input range (ITripMAX = VREF / (AV × RS)). |
| 5 | VBB | power_in | Load supply voltage, 8 to 40 V operating range; decouple with a 100 µF electrolytic in parallel with a lower-value ceramic capacitor. |
| 6 | OUT1 | output | DMOS full bridge output 1, with up to 2 A continuous output current. |
| 7 | LSS | passive | Power return, connection for the current sense resistor to ground; limit the sense voltage to ±500 mV. |
| 8 | OUT2 | output | DMOS full bridge output 2, with up to 2 A continuous output current. |
| 9 | PAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems, LLC |
| Package | SOIC-8-EP |
| Category | Power Management ICs |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Load Supply Voltage Range | VBB | 8 | 40 | V | 3 | ||
| Sink+Source Total RDS(on) | RDS(on) | 0.8 | 1 | Ω | IOUT = /1.5 A/, TJ = 25°C | 3 | |
| Sink+Source Total RDS(on) | RDS(on) | 1.3 | 1.6 | Ω | IOUT = /1.5 A/, TJ = 125°C | 3 | |
| Load Supply Current | IBB | 10 | mA | fPWM < 30 kHz | 3 | ||
| Load Supply Current standby | IBB | 10 | µA | Low Power Standby mode | 3 | ||
| Body Diode Forward Voltage (source) | Vf | 1.5 | V | Source diode, If = -1.5 A | 3 | ||
| Body Diode Forward Voltage (sink) | Vf | 1.5 | V | Sink diode, If = 1.5 A | 3 | ||
| Logic Input High Voltage | VIN(1) | 2 | V | INx pins | 3 | ||
| Logic Input Low Voltage | VIN(0) | 0.8 | V | INx pins | 3 | ||
| Standby Input Voltage | VIN(STANDBY) | 0.4 | V | INx pins, Low Power Standby mode | 3 | ||
| Logic Input Current high | IIN(1) | 40 | 100 | µA | INx pins, VIN = 2.0 V | 3 | |
| Logic Input Current low | IIN(0) | 16 | 40 | µA | INx pins, VIN = 0.8 V | 3 | |
| Input Hysteresis | VHYS | 250 | 550 | mV | 3 | ||
| Logic Input Pull-Down Resistance | RLOGIC(PD) | 50 | kΩ | VIN = 0 V = IN1 = IN2 | 3 | ||
| Crossover Delay | tCOD | 50 | 400 | 500 | ns | 3 | |
| VREF Input Voltage Range | VREF | 0 | 5 | V | 3 | ||
| Current Gain | AV | 9.5 | 10.5 | V/V | VREF / ISS, VREF = 5 V | 3 | |
| Current Gain | AV | 9 | 10 | V/V | VREF / ISS, VREF = 2.5 V | 3 | |
| Current Gain | AV | 8 | 10 | V/V | VREF / ISS, VREF = 1 V | 3 | |
| Blank Time | tBLANK | 2 | 3 | 4 | µs | 3 | |
| Constant Off-time | toff | 16 | 25 | 34 | µs | 3 | |
| Standby Timer | tst | 1 | 1.5 | ms | IN1 = IN2 < VIN(STANDBY) | 3 | |
| Power-Up Delay | tpu | 30 | µs | 3 | |||
| UVLO Enable Threshold | VBBUVLO | 7 | 7.5 | 7.95 | V | VBB increasing | 3 |
| UVLO Hysteresis | VBBUVLOhys | 500 | mV | 3 | |||
| Thermal Shutdown Temperature | TJTSD | 160 | °C | Temperature increasing | 3 | ||
| Thermal Shutdown Hysteresis | TTSDhys | 20 | °C | Recovery = TJTSD, TTSDhys | 3 | ||
| Overcurrent Protection Limit | IOCP | 2.5 | 6.5 | A | 3 | ||
| Overcurrent Protection Pulse Width | tOCP | 1 | 4 | µs | 3 | ||
| Load Supply Voltage | VBB | 40 | V | 2 | |||
| Logic I/O Voltage Range | VIN | -0.3 | 6 | V | 2 | ||
| VREF Input Voltage Range | VREF | -0.3 | 6 | V | 2 | ||
| Sense Voltage (LSS pin) | VS | -0.5 | 0.5 | V | 2 | ||
| Motor Outputs Voltage | VOUT | -2 | 42 | V | 2 | ||
| Output Current | IOUT | 2 | A | Duty cycle = 100% | 2 | ||
| Transient Output Current | iOUT | 6 | A | TW < 500 ns | 2 | ||
| Operating Temperature Range | TA | -40 | 85 | °C | Temperature Range E | 2 | |
| Maximum Junction Temperature | TJ(max) | 150 | °C | 2 | |||
| Storage Temperature Range | Tstg | -55 | 150 | °C | 2 | ||
| FLTn Sink Current | IFLTN | 10 | mA | 2 | |||
| Package Thermal Resistance | RθJA | 35 | ºC/W | LJ package, on 4-layer PCB based on JEDEC standard | 2 | ||
| Package Thermal Resistance | RθJA | 62 | ºC/W | LJ package, on 2-layer PCB with 0.8 in2. 2-oz. copper each side | 2 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | 8-pin SOICN package (suffix LJ). Both packages have an exposed thermal pad, and are lead (Pb) free, with 100% matte tin | 1 |
CAD (KiCad official)
- Symbol:
A4953ELJTR-T - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOIC-8-EP (KiCad packages3D, STEP)
- 3D model files:
a4953eljtr-t-etched.step/a4953eljtr-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);a4953eljtr-t.step/a4953eljtr-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Allegro MicroSystems, LLC datasheet (11 pp, sha256
9b8c176dcbf20a12, retrieved 2026-10-22, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# A4953ELJTR-T
**Allegro MicroSystems, LLC** · Motor Driver ICs · SOIC-8-EP
A4953ELJTR-T from Allegro MicroSystems, LLC, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground; a star ground should be located as close to the device as possible. |
| 2 | IN2 | input | Logic input 2 for bridge control (VIN(1) min 2.0 V, VIN(0) max 0.8 V, 50 kΩ typ internal pull-down); both inputs low for over 1 ms enters Low Power Standby mode. |
| 3 | IN1 | input | Logic input 1 for bridge control (VIN(1) min 2.0 V, VIN(0) max 0.8 V, 50 kΩ typ internal pull-down); both inputs low for over 1 ms enters Low Power Standby mode. |
| 4 | VREF | power_in | Analog input setting the PWM current limit, 0 to 5 V input range (ITripMAX = VREF / (AV × RS)). |
| 5 | VBB | power_in | Load supply voltage, 8 to 40 V operating range; decouple with a 100 µF electrolytic in parallel with a lower-value ceramic capacitor. |
| 6 | OUT1 | output | DMOS full bridge output 1, with up to 2 A continuous output current. |
| 7 | LSS | passive | Power return, connection for the current sense resistor to ground; limit the sense voltage to ±500 mV. |
| 8 | OUT2 | output | DMOS full bridge output 2, with up to 2 A continuous output current. |
| 9 | PAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems, LLC |
| Package | SOIC-8-EP |
| Category | Power Management ICs |
| Pins | 9 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Load Supply Voltage Range | VBB | 8 | | 40 | V | | 3 |
| Sink+Source Total RDS(on) | RDS(on) | | 0.8 | 1 | Ω | IOUT = /1.5 A/, TJ = 25°C | 3 |
| Sink+Source Total RDS(on) | RDS(on) | | 1.3 | 1.6 | Ω | IOUT = /1.5 A/, TJ = 125°C | 3 |
| Load Supply Current | IBB | | 10 | | mA | fPWM < 30 kHz | 3 |
| Load Supply Current standby | IBB | | | 10 | µA | Low Power Standby mode | 3 |
| Body Diode Forward Voltage (source) | Vf | | | 1.5 | V | Source diode, If = -1.5 A | 3 |
| Body Diode Forward Voltage (sink) | Vf | | | 1.5 | V | Sink diode, If = 1.5 A | 3 |
| Logic Input High Voltage | VIN(1) | 2 | | | V | INx pins | 3 |
| Logic Input Low Voltage | VIN(0) | | | 0.8 | V | INx pins | 3 |
| Standby Input Voltage | VIN(STANDBY) | | | 0.4 | V | INx pins, Low Power Standby mode | 3 |
| Logic Input Current high | IIN(1) | | 40 | 100 | µA | INx pins, VIN = 2.0 V | 3 |
| Logic Input Current low | IIN(0) | | 16 | 40 | µA | INx pins, VIN = 0.8 V | 3 |
| Input Hysteresis | VHYS | | 250 | 550 | mV | | 3 |
| Logic Input Pull-Down Resistance | RLOGIC(PD) | | 50 | | kΩ | VIN = 0 V = IN1 = IN2 | 3 |
| Crossover Delay | tCOD | 50 | 400 | 500 | ns | | 3 |
| VREF Input Voltage Range | VREF | 0 | | 5 | V | | 3 |
| Current Gain | AV | 9.5 | | 10.5 | V/V | VREF / ISS, VREF = 5 V | 3 |
| Current Gain | AV | 9 | | 10 | V/V | VREF / ISS, VREF = 2.5 V | 3 |
| Current Gain | AV | 8 | | 10 | V/V | VREF / ISS, VREF = 1 V | 3 |
| Blank Time | tBLANK | 2 | 3 | 4 | µs | | 3 |
| Constant Off-time | toff | 16 | 25 | 34 | µs | | 3 |
| Standby Timer | tst | | 1 | 1.5 | ms | IN1 = IN2 < VIN(STANDBY) | 3 |
| Power-Up Delay | tpu | | | 30 | µs | | 3 |
| UVLO Enable Threshold | VBBUVLO | 7 | 7.5 | 7.95 | V | VBB increasing | 3 |
| UVLO Hysteresis | VBBUVLOhys | | 500 | | mV | | 3 |
| Thermal Shutdown Temperature | TJTSD | | 160 | | °C | Temperature increasing | 3 |
| Thermal Shutdown Hysteresis | TTSDhys | | 20 | | °C | Recovery = TJTSD, TTSDhys | 3 |
| Overcurrent Protection Limit | IOCP | 2.5 | | 6.5 | A | | 3 |
| Overcurrent Protection Pulse Width | tOCP | 1 | | 4 | µs | | 3 |
| Load Supply Voltage | VBB | | | 40 | V | | 2 |
| Logic I/O Voltage Range | VIN | -0.3 | | 6 | V | | 2 |
| VREF Input Voltage Range | VREF | -0.3 | | 6 | V | | 2 |
| Sense Voltage (LSS pin) | VS | -0.5 | | 0.5 | V | | 2 |
| Motor Outputs Voltage | VOUT | -2 | | 42 | V | | 2 |
| Output Current | IOUT | | | 2 | A | Duty cycle = 100% | 2 |
| Transient Output Current | iOUT | | | 6 | A | TW < 500 ns | 2 |
| Operating Temperature Range | TA | -40 | | 85 | °C | Temperature Range E | 2 |
| Maximum Junction Temperature | TJ(max) | | | 150 | °C | | 2 |
| Storage Temperature Range | Tstg | -55 | | 150 | °C | | 2 |
| FLTn Sink Current | IFLTN | | | 10 | mA | | 2 |
| Package Thermal Resistance | RθJA | | 35 | | ºC/W | LJ package, on 4-layer PCB based on JEDEC standard | 2 |
| Package Thermal Resistance | RθJA | | 62 | | ºC/W | LJ package, on 2-layer PCB with 0.8 in2. 2-oz. copper each side | 2 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | | tin | 8-pin SOICN package (suffix LJ). Both packages have an exposed thermal pad, and are lead (Pb) free, with 100% matte tin | 1 |
## CAD (KiCad official)
- Symbol: `A4953ELJTR-T`
- Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm`
- 3D model: SOIC-8-EP (KiCad packages3D, STEP)
- 3D model files: `a4953eljtr-t-etched.step` / `a4953eljtr-t-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `a4953eljtr-t.step` / `a4953eljtr-t.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Allegro MicroSystems, LLC datasheet](docs/a4953eljtr-t-datasheet.pdf) (11 pp, sha256 `9b8c176dcbf20a12`, retrieved 2026-10-22, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/a4953eljtr-t-datasheet.pdf)