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A4933KJPTR-T

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Allegro MicroSystems, LLC Motor Driver ICs, LQFP-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management icsa4933kjptr-tfactory-2.0.0extractor-text

Verified A4933KJPTR-T

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier lcsc, 49 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: A4933KJPTR-T · LQFP-48-EP(7x7) · 49 pins
  • ✓copper: 49 copper pads, none touching another net
  • ✓datasheet: all 49 pin names found in the 25-page datasheet
  • ✓distributor: lcsc C2150765, digikey 620-A4933KJPTR-TTR-ND, mouser 250-A4933KJPTR-T
  • ✓family: LQFP-48-1EP_7x7mm_P0.5mm_EP3.6x3.6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-5e4g18cv/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 49 pins = 49 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 49 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ a4933kjptr-t.kicad_sym✓ a4933kjptr-t.kicad_mod✓ a4933kjptr-t.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs Publish 0.1.0 · Ray 3d ago
viewers a4933kjptr-t: viewers · Ray 3d ago
a4933kjptr-t-etched.glb Publish 0.1.0 · Ray 3d ago
a4933kjptr-t-etched.step a4933kjptr-t: factory component page (tier=lcsc) · Ray 3d ago
a4933kjptr-t-hero.glb a4933kjptr-t: hero GLB from the etched model (keeps the MPN mark) · Ray 3d ago
a4933kjptr-t-hero.overlay.json Publish 0.1.0 · Ray 3d ago
a4933kjptr-t.glb Publish 0.1.0 · Ray 3d ago
a4933kjptr-t.kicad_mod Publish 0.1.0 · Ray 3d ago
a4933kjptr-t.kicad_sym Publish 0.1.0 · Ray 3d ago
a4933kjptr-t.lbr Publish 0.1.0 · Ray 3d ago
a4933kjptr-t.step Publish 0.1.0 · Ray 3d ago
package.json Publish 0.1.0 · Ray 3d ago
page.json Set visibility: public · Ray 3d ago
README.md Publish 0.1.0 · Ray 3d ago
verification.json Verified: Published by the parts factory: tier lcsc, 49 pins · Ray 3d ago

A4933KJPTR-T

Allegro MicroSystems, LLC · Motor Driver ICs · LQFP-48-EP(7x7)

A4933KJPTR-T from Allegro MicroSystems, LLC, in a LQFP-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No internal connection; connect to AGND.
2 RESET input Standby mode control input.
3 ESF input Enable Stop on Fault input.
4 FF2 bidirectional Fault Flag 2 and serial clock input.
5 FF1 bidirectional Fault Flag 1 and serial data output.
6 ALO input Control input for phase A low-side gate drive.
7 AHI input Control input for phase A high-side gate drive.
8 BHI input Control input for phase B high-side gate drive.
9 BLO input Control input for phase B low-side gate drive.
10 CLO input Control input for phase C low-side gate drive.
11 CHI input Control input for phase C high-side gate drive.
12 PWML input Low-side PWM input.
13 CCEN input Cross-conduction enable input.
14 PWMH input High-side PWM input.
15 COAST input Coast input.
16 CSOUT output Current sense amplifier output.
17 VDD power_in Logic supply input.
18 CSN input Current sense negative input.
19 CSP input Current sense positive input.
20 VDSTH input Fault threshold voltage input for the VDS monitor.
21 LSS passive Low-side source connection.
22 GLC output Low-side gate drive output for phase C.
23 AGND power_in Analog ground.
24 NC unconnected No internal connection; connect to AGND.
25 NC unconnected No internal connection; connect to AGND.
26 SC passive Motor connection for phase C.
27 GHC output High-side gate drive output for phase C.
28 CC passive Bootstrap capacitor connection for phase C.
29 GLB output Low-side gate drive output for phase B.
30 SB passive Motor connection for phase B.
31 GHB output High-side gate drive output for phase B.
32 CB passive Bootstrap capacitor connection for phase B.
33 GLA output Low-side gate drive output for phase A.
34 SA passive Motor connection for phase A.
35 NC unconnected No internal connection; connect to AGND.
36 NC unconnected No internal connection; connect to AGND.
37 NC unconnected No internal connection; connect to AGND.
38 GHA output High-side gate drive output for phase A.
39 CA passive Bootstrap capacitor connection for phase A.
40 VREG power_out Gate drive supply output.
41 VDRAIN input High-side drain voltage sense input.
42 NC unconnected No internal connection; connect to AGND.
43 CP2 passive Pump capacitor connection 2.
44 CP1 passive Pump capacitor connection 1.
45 PGND power_in Power ground.
46 VBB power_in Main power supply input.
47 AGND power_in Analog ground.
48 RDEAD passive Dead time setting input.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Allegro MicroSystems, LLC
Package LQFP-48-EP(7x7)
Category Power Management ICs
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Load Supply Voltage Functional Operating Range VBB 5.5 50 V Functional operating range 4
Load Supply Voltage VBB -0.3 50 V With respect to AGND 2
Logic Supply Voltage VDD -0.3 7 V With respect to AGND 2
VREG VREG -0.3 16 V With respect to AGND 2
CP1 and CP2 CP1, CP2 -0.3 16 V With respect to AGND 2
Logic Inputs and Outputs -0.3 6.5 V With respect to AGND 2
CSP and CSN CSP, CSN -4 6.5 V With respect to AGND 2
LSS LSS -4 6.5 V With respect to AGND 2
CSO and VDSTH CSO, VDSTH -0.3 6.5 V With respect to AGND 2
SA, SB, and SC SA, SB, SC -5 55 V With respect to AGND 2
RDEAD RDEAD -0.3 6.5 V With respect to AGND 2
VDRAIN VDRAIN -5 55 V With respect to AGND 2
GLA, GLB, and GLC GLA, GLB, GLC -5 16 V With respect to AGND 2
Operating Temperature Range TA -40 150 ºC Range K 2
Junction Temperature TJ(max) 150 ºC 2
Transient Junction Temperature TtJ 175 ºC Overtemperature event not exceeding 10 s, lifetime duration not exceeding 10 h, guaranteed by design characterization 2
Storage Temperature Range Tstg -55 150 ºC 2
Load Supply Quiescent Current IBBQ 10 14 mA RESET = high, outputs = low, VBB = 12 V 4
Load Supply Quiescent Current (sleep) IBBS 10 μA RESET = low, Sleep mode, VBB = 12 V 4
Logic Supply Voltage VDD 3 5.5 V 4
Logic Supply Quiescent Current IDDQ 4 6 mA RESET = high, outputs = low 4
Logic Supply Quiescent Current (reset) IDDS 10 μA RESET = low 4
VREG Output Voltage VREG 9 13 13.8 V VBB > 9 V, IREG = 0 to 50 mA 4
VREG Output Voltage VREG 8.5 V 6 V < VBB ≤ 7.5 V, IREG = 0 to 17 mA 4
VREG Output Voltage VREG 7.5 9.5 V 5.5 V < VBB ≤ 6 V, IREG < 13 mA 4
Bootstrap Diode Forward Voltage VfBOOT 0.4 0.7 1 V ID = 10 mA 4
Bootstrap Diode Forward Voltage VfBOOT 0.6 1 1.2 V ID = 100 mA 4
Bootstrap Diode Current Limit IDBOOT 500 1000 1500 mA 4
Pullup On Resistance RDS(on)UP 3 4 6 Ω TJ = 25°C, IGHx = -300 mA 4
Pullup On Resistance RDS(on)UP 5 6.5 8 Ω TJ = 150°C, IGHx = -300 mA 4
Pulldown On Resistance RDS(on)DN 1 1.5 2 Ω TJ = 25°C, IGLx = 300 mA 4
Pulldown On Resistance RDS(on)DN 1.5 2 3 Ω TJ = 150°C, IGLx = 300 mA 4
Turn-Off Propagation Delay tP(off) 60 90 130 ns Input change to unloaded gate output change 4
Turn-On Propagation Delay tP(on) 60 90 130 ns Input change to unloaded gate output change 4
Dead Time tDEAD 815 960 1110 ns RDEAD = 30 kΩ 5
FF1 and FF2 Fault Output VFF(L) 0.4 V IFF = 1 mA, fault not present 5
FF1 and FF2 Fault Output Leakage Current IFF(H) -1 1 μA VFF = 5 V, fault present 5
RDEAD Input Low Voltage VDEAD(L) 0.2 V 5
RDEAD Current IDEAD -200 -70 μA RDEAD = GND 5
Input Hysteresis VINhys 300 500 mV 5
RESET Pulse Time tRES 0.1 3.5 μs 5
FF2 Clock Low to Valid Data Delay tDF 100 ns 5
FF2 Clock High Time tHF 500 ns 5
Input Offset Voltage VIOS -10 10 mV CSP = CSN = 0 V 5
Input Common Mode Range CMR -1.5 4 V CSP = CSN 5
Closed Loop Gain AVclos 5 V/V 40 mV< VID < 175 mV, VCM in range 6
Output Current Sink ICSsink 1 mA VID = -400 mV, VCSOUT = 1.5 V 6
VREG Undervoltage Lockout Threshold (rising) VREGUVon 7.5 8 8.5 V VREG rising 6
VREG Undervoltage Lockout Threshold (falling) VREGUVoff 6.75 7.25 7.75 V VREG falling 6
Bootstrap Undervoltage Threshold VBOOTUV 59 69 %VREG Cx with respect to Sx 6
VDD Undervoltage Turn-Off Threshold VDDUV 2.45 2.7 2.85 V VDD falling 6
VDSTH Input Range VDSTH 0.1 2 V 6
Short-to-Ground Threshold Offset VSTGO -100 100 mV High-side on, VDSTH ≥ 1 V 6
Short-to-Ground Threshold Offset VSTGO -150 150 mV High-side on, VDSTH < 1 V 6
Overtemperature Fault Flag Threshold TJF 150 170 ºC Temperature increasing 6
Junction-to-ambient Thermal Resistance (4-layer PCB) RθJA 23 ºC/W 4-layer PCB based on JEDEC standard 2
Junction-to-ambient Thermal Resistance (2-layer PCB) RθJA 44 ºC/W 2-layer PCB with 3 in.2 of copper area each side 2
Junction-to-exposed-pad Thermal Resistance RθJP 2 ºC/W 2

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin lead (Pb) free with 100% matte tin leadframe plating. Description (continued) 2

CAD (KiCad official)

  • Symbol: A4933KJPTR-T
  • Footprint: Package_QFP:LQFP-48-1EP_7x7mm_P0.5mm_EP3.6x3.6mm
  • 3D model: LQFP-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: a4933kjptr-t-etched.step / a4933kjptr-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); a4933kjptr-t.step / a4933kjptr-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Allegro MicroSystems, LLC datasheet (25 pp, sha256 6e13e125f72c0af8, retrieved 2026-10-30, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF