A4910KJPTR-T from Allegro MicroSystems, LLC, in a LQFP-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SA	passive	Motor connection for phase A, sensing the switched load voltage and connected to the negative side of the bootstrap capacitor (abs max VCx - 16 V to VCx + 0.3 V).
2	CA	passive	Bootstrap capacitor connection for phase A and positive supply for the high-side gate driver (abs max -0.3 V to VREG + 50 V).
3	VREG	power_out	Gate drive supply output, regulated nominally 13 V, requiring a storage capacitor to supply low-side drivers and bootstrap charging (abs max -0.3 to 16 V).
4	CP2	passive	Charge pump capacitor terminal; connect a minimum 220 nF, typically 470 nF, capacitor between CP1 and CP2.
5	CP1	passive	Charge pump capacitor terminal; connect a minimum 220 nF, typically 470 nF, capacitor between CP1 and CP2 (abs max -0.3 to 16 V).
6	PGND	power_in	Digital and power ground, to be connected to supply ground and AGND.
7	VBB	power_in	Main power supply for internal regulators and charge pump, operating 7 to 50 V (functional down to 5.5 V), connected through reverse voltage protection and decoupled.
8	VBRG	input	Sense input to the top of the external MOSFET bridge for measuring the drain voltage of the high-side MOSFETs (abs max -5 to 55 V).
9	AGND	power_in	Analog reference ground, quiet return for measurement and input references, connected to PGND.
10	VDD	power_in	Logic supply of 3 to 5.5 V, decoupled with a 100 nF capacitor (abs max -0.3 to 6 V).
11	COASTn	input	Active-low input that forces all gate drive outputs low, turning off all external MOSFETs and overriding all other gate control inputs and registers.
12	RESETn	input	Standby mode control: pulsing low resets faults and holding low longer than tRSD forces sleep mode; can be pulled to VBB with a 20 to 33 kΩ resistor.
13	STRn	input	Serial strobe (chip select) input; when high, SCK and SDI activity is ignored and SDO is high impedance.
14	SCK	input	Serial clock input; data is latched from SDI on the rising edge, with 16 rising edges per write, and SCK must be held high when STRn changes.
15	SDI	input	Serial data input, 16-bit word, MSB first.
16	SDO	tri_state	Serial data output, high impedance when STRn is high, outputting the fault flag as soon as STRn goes low (abs max -0.3 to VDD + 0.3 V).
17	DIAG	output	Programmable diagnostic output selecting fault flag (default), temperature, clock, or VDS threshold.
18	AHI	input	Control input for high side of phase A, logically ORed with the Run register bit to control GHA.
19	ALO	input	Control input for low side of phase A, logically ORed with the Run register bit to control GLA.
20	BHI	input	Control input for high side of phase B, logically ORed with the Run register bit to control GHB.
21	BLO	input	Control input for low side of phase B, logically ORed with the Run register bit to control GLB.
22	CHI	input	Control input for high side of phase C, logically ORed with the Run register bit to control GHC.
23	CLO	input	Control input for low side of phase C, logically ORed with the Run register bit to control GLC.
24	OPAP	input	Uncommitted operational amplifier non-inverting input (abs max -0.3 to 6.5 V).
25	OPAM	input	Uncommitted operational amplifier inverting input (abs max -0.3 to 6.5 V).
26	OPAO	output	Uncommitted operational amplifier output (abs max -0.3 to VDD + 0.3 V).
27	CSCP	input	Phase C current-sense amplifier positive input (abs max -4 to 6.5 V).
28	CSCM	input	Phase C current-sense amplifier negative input (abs max -4 to 6.5 V).
29	CSCO	output	Phase C current-sense amplifier output (abs max -0.3 to VDD + 0.3 V).
30	CSBP	input	Phase B current-sense amplifier positive input (abs max -4 to 6.5 V).
31	CSBM	input	Phase B current-sense amplifier negative input (abs max -4 to 6.5 V).
32	CSBO	output	Phase B current-sense amplifier output (abs max -0.3 to VDD + 0.3 V).
33	CSAP	input	Phase A current-sense amplifier positive input (abs max -4 to 6.5 V).
34	CSAM	input	Phase A current-sense amplifier negative input (abs max -4 to 6.5 V).
35	CSAO	output	Phase A current-sense amplifier output (abs max -0.3 to VDD + 0.3 V).
36	LSSC	passive	Low-side source return for phase C gate discharge, connected to the low-side MOSFET source through a low-impedance track (abs max VREG - 16 to 18 V).
37	GLC	output	Low-side gate drive output for phase C external N-channel MOSFET (abs max VREG - 16 to 18 V).
38	GHC	output	High-side gate drive output for phase C external N-channel MOSFET (abs max VCx - 16 to VCx + 0.3 V).
39	SC	passive	Motor connection for phase C, sensing the switched load voltage and connected to the negative side of the bootstrap capacitor.
40	CC	passive	Bootstrap capacitor connection for phase C and positive supply for the high-side gate driver (abs max -0.3 to VREG + 50 V).
41	LSSB	passive	Low-side source return for phase B gate discharge, connected to the low-side MOSFET source through a low-impedance track (abs max VREG - 16 to 18 V).
42	GLB	output	Low-side gate drive output for phase B external N-channel MOSFET (abs max VREG - 16 to 18 V).
43	GHB	output	High-side gate drive output for phase B external N-channel MOSFET (abs max VCx - 16 to VCx + 0.3 V).
44	SB	passive	Motor connection for phase B, sensing the switched load voltage and connected to the negative side of the bootstrap capacitor.
45	CB	passive	Bootstrap capacitor connection for phase B and positive supply for the high-side gate driver (abs max -0.3 to VREG + 50 V).
46	LSSA	passive	Low-side source return for phase A gate discharge, connected to the low-side MOSFET source through a low-impedance track (abs max VREG - 16 to 18 V).
47	GLA	output	Low-side gate drive output for phase A external N-channel MOSFET (abs max VREG - 16 to 18 V).
48	GHA	output	High-side gate drive output for phase A external N-channel MOSFET (abs max VCx - 16 to VCx + 0.3 V).
49	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Allegro MicroSystems, LLC
Package	LQFP-48-EP(7x7)
Category	Power Management ICs
Pins	49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Load Supply Voltage	VBB	-0.3		50	V		2
Logic Supply Voltage	VDD	-0.3		6	V		2
Terminal VREG	VREG	-0.3		16	V		2
Terminal CP1	VCP1	-0.3		16	V		2
Logic Inputs		-0.3		6	V	STRn, SDI, SCK, RESETn, COASTn, xHI, xLO terminals	2
Sense Amplifier Inputs		-4		6.5	V	CSAP, CSAM, CSBP, CSBM, CSCP, CSCM terminals	2
Operational Amplifier Inputs		-0.3		6.5	V	OPAP and OPAM terminals	2
Terminal VBRG	VBRG	-5		55	V		2
Ambient Operating Temperature Range	TA	-40		150	°C	Limited by power dissipation	2
Maximum Junction Temperature	TJ(max)			150	°C	Continuous	2
Maximum Junction Temperature, overtemperature event	TJ(max)			175	°C	Overtemperature event not exceeding 10 seconds, lifetime duration not exceeding 10 hours	2
Storage Temperature Range	Tstg	-55		150	°C		2
Package Thermal Resistance (Junction to Ambient)	RθJA		23		°C/W	On 4-layer PCB based on JEDEC standard	3
Package Thermal Resistance (Junction to Ambient)	RθJA		44		°C/W	On 2-layer PCB with 3 in.2 of copper area each side	3
Package Thermal Resistance (Junction to Pad)	RθJP		2		°C/W		3
VBB Functional Operating Range	VBB	5.5		50	V		6
VBB Quiescent Current	IBBQ		10	14	mA	RESETn = high, outputs low, VBB = 12 V	6
VBB Quiescent Current, sleep	IBBS			10	µA	RESETn = low, sleep mode, VBB = 12 V	6
VDD Logic Supply	VDD	3		5.5	V		6
VDD Quiescent Current	IDDQ		10	13	mA	RESETn = high, outputs low	6
VDD Quiescent Current, sleep	IDDS			10	µA	RESETn = low, sleep mode	6
VREG Output Voltage	VREG	9	13	13.8	V	VBB > 9 V, IREG = 0 to 30 mA	6
VREG Output Voltage	VREG	7.9			V	6 V < VBB ≤ 7.5 V, IREG = 0 to 15 mA	6
VREG Output Voltage	VREG	7.9	9.5		V	5.5 V < VBB ≤ 6 V, IREG < 9 mA	6
Bootstrap Diode Forward Voltage	VfBOOT	0.4	0.7	1	V	ID = 10 mA	6
Bootstrap Diode Forward Voltage	VfBOOT	1.5	2.2	2.8	V	ID = 100 mA	6
Bootstrap Diode Resistance	rD	6	11	22	Ω	rD(100 mA) = (VfBOOT(150 mA), VfBOOT(50mA))/ 100 mA	6
Bootstrap Diode Current Limit	IDBOOT	250	500	750	mA		6
High-Side Gate Drive Static Load Resistance	RGSH	250			kΩ		6
System Clock Period	tOSC	45	50	55	ns		6
Pull-Up On-Resistance	RDS(on)UP	5	8	11	Ω	TJ = 25°C, IGHx = -150 mA	6
Pull-Up On-Resistance	RDS(on)UP	10	15	20	Ω	TJ = 150°C, IGHx = -150 mA	6
Pull-Down On-Resistance	RDS(on)DN	1.7	2.5	3.1	Ω	TJ = 25°C, IGLx = 150 mA	6
Pull-Down On-Resistance	RDS(on)DN	2.9	4	5	Ω	TJ = 150°C, IGLx = 150 mA	6
Turn-Off Propagation Delay	tP(off)	60	90	140	ns	Input change to unloaded gate output change (see figure 5)	7
Turn-On Propagation Delay	tP(on)	50	80	130	ns	Input change to unloaded gate output change (see figure 5)	7
Propagation Delay Matching (Phase-to-Phase)	∆tPP		5	15	ns	Same phase change, DT[6..0] = 0	7
Propagation Delay Matching (On-to-Off)	∆tOO		15	30	ns	Single phase, DT[6..0] = 0	7
Propagation Delay Matching (GHx-to-GLx)	∆tHL			20	ns	Rising to rising edges, falling to falling edges, DT[6..0] = 0	7
Input Hysteresis	VIhys	200	350		mV	RESETn pin	7
Input Hysteresis	VIhys	250	500		mV	All other logic pins	7
Input Pull-Up Resistor	RPU	30	50	70	kΩ	STRn	7
Input Pull-Down Resistor	RPD	30	50	70	kΩ	COASTn, RESETn, SCK, SDI, AHI, ALO, BHI, BLO, CHI, and CLO pins	7
Output Low Voltage	VOL		0.2	0.4	V	IOL= 1 mA	7
Output Leakage (SDO pin)	ISDOlkg	-1		1	µA	0 V < VSDO < VDD, STRn = 1	7
Reset Pulse Width	tRST	0.2		4.5	µs		7
Input Offset Voltage (current sense amplifier)	VIOS(SA)	-10		10	mV		8
VREG Undervoltage Lockout, rising	VREGON	7.6	7.95	8.2	V	VREG rising	10
VREG Undervoltage Lockout, falling	VREGOFF	6.9	7.18	7.4	V	VREG falling	10
Bootstrap Undervoltage	VBOOTUV	60		74	%VREG	Cx with respect to Sx	10
VDD Undervoltage Turn Off	VDDUV	2.45	2.7	2.85	V	VDD falling	10
Fault Blanking Time	tBL	2.8	3.2	3.6	µs	Default power-up state	10
VBRG Input Voltage	VBRG	5.5		50	V		10
Hot Temperature Warning Threshold	TJWH	125	135	145	°C	Temperature increasing	10
Overtemperature Flag	TJF	155	170		°C	Temperature increasing	10
VDS Threshold	VDSTH		800		mV	Default power-up level	10
Turn-On Time	tr		190		ns	CLOAD = 10 nF, 20% to 80% points	6

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts		tin	with exposed thermal pad (suffix JP). It is lead (Pb) free, with 100% matte-tin leadframe plating.	2

CAD (KiCad official)

Symbol: A4910KJPTR-T
Footprint: Package_QFP:LQFP-48-1EP_7x7mm_P0.5mm_EP3.6x3.6mm
3D model: LQFP-48-EP(7x7) (KiCad packages3D, STEP)
3D model files: a4910kjptr-t-etched.step / a4910kjptr-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); a4910kjptr-t.step / a4910kjptr-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Allegro MicroSystems, LLC datasheet (36 pp, sha256 696bf2e310245234, retrieved 2026-10-30, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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A4910KJPTR-T

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