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93LC56C-I

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Microchip Tech EEPROM, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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93LC56C-I

Microchip Tech · EEPROM · SOIC-8

93LC56C-I from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS input A high level selects the device and a low level deselects it and forces it into Standby mode; CS must be low for 250 ns minimum (TCSL) between consecutive instructions.
2 CLK input Serial Clock: opcodes, address and data bits are clocked in on the positive edge of CLK, and data bits are clocked out on its positive edge; CLK is a don't care while CS is low.
3 DI input Data In: clocks in the Start bit, opcode, address and data synchronously with the CLK input.
4 DO output Data Out: outputs read data synchronously with CLK (TPD after the positive CLK edge) and provides Ready/Busy status during erase and write cycles when CS is brought high after being low for TCSL; it is High-Z when CS is held low through the cycle.
5 VSS power_in Ground reference for the device.
6 ORG input Memory organization select on the 93XX56C: tied to VCC or logic HI selects x16 organization, tied to VSS or logic LO selects x8, and it must be tied to a valid logic level for proper operation (this pin is NC on A/B devices).
7 NC unconnected No internal connection on this package for the 93LC56C.
8 VCC power_in Power supply; the 93LC56C operates from 2.5 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package SOIC-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
High-level input voltage VIH1 2 V VCC ≥ 2.7V 3
High-level input voltage VIH2 0.7 x VCC VCC < 2.7V 3
Low-level input voltage VIL1 -0.3 0.8 V VCC ≥ 2.7V 3
Low-level input voltage VIL2 -0.3 0.2 x VCC VCC < 2.7V 3
Low-level output voltage Vol1 0.4 V IOL = 2.1 mA, VCC = 4.5V 3
Low-level output voltage Vol2 0.2 V IOL = 100 µA, VCC = 2.5V 3
High-level output voltage VOH1 2.4 V IOH = -400 µA, VCC = 4.5V 3
Input leakage current ILI -1 1 µA VIN = VSS or VCC 3
Output leakage current ILO -1 1 µA VOUT = VSS or VCC 3
Pin capacitance (all inputs/outputs) CIN, COUT 7 pF VIN/VOUT = 0V (Note 1); TA = 25°C, FCLK = 1 MHz 3
Standby current ICCS 1 µA I-Temp; CLK = CS = 0V; ORG = DI = VSS or VCC 3
VCC voltage detect VPOR 1.5 V 93AA56A/B/C, 93LC56A/B/C (Note 1) 3
Supply voltage (VCC) absolute maximum VCC 7 V 3
All inputs and outputs w.r.t. VSS -0.6 V 3
Storage temperature -65 150 °C 3
Ambient temperature with power applied -40 125 °C 3
Supply voltage (VCC) VCC 2.5 5.5 V 93LC56C (Device Selection Table) 1
Ambient temperature, Industrial (I) TA -40 85 °C Industrial (I) range 3
Clock frequency FCLK 3 MHz 4.5V ≤ VCC < 5.5V, 93XX56C only 4
Clock frequency FCLK 2 MHz 2.5V ≤ VCC < 5.5V 4
Clock high time TCKH 200 ns 4.5V ≤ VCC < 5.5V, 93XX56C only 4
Clock high time TCKH 250 ns 2.5V ≤ VCC < 5.5V 4
Clock low time TCKL 100 ns 4.5V ≤ VCC < 5.5V, 93XX56C only 4
Clock low time TCKL 200 ns 2.5V ≤ VCC < 5.5V 4
Chip select setup time TCSS 50 ns 4.5V ≤ VCC < 5.5V 4
Chip select setup time TCSS 100 ns 2.5V ≤ VCC < 4.5V 4
Chip select hold time TCSH 0 ns 1.8V ≤ VCC < 5.5V 4
Chip select low time TCSL 250 ns 1.8V ≤ VCC < 5.5V 4
Data input setup time TDIS 50 ns 4.5V ≤ VCC < 5.5V, 93XX56C only 4
Data input setup time TDIS 100 ns 2.5V ≤ VCC < 5.5V 4
Data input hold time TDIH 50 ns 4.5V ≤ VCC < 5.5V, 93XX56C only 4
Data input hold time TDIH 100 ns 2.5V ≤ VCC < 5.5V 4
Data output delay time TPD 200 ns 4.5V ≤ VCC < 5.5V, CL = 100 pF 4
Data output delay time TPD 250 ns 2.5V ≤ VCC < 4.5V, CL = 100 pF 4
Data output disable time TCZ 100 ns 4.5V ≤ VCC < 5.5V (Note 1) 4
Data output disable time TCZ 200 ns 1.8V ≤ VCC < 4.5V (Note 1) 4
Status valid time TSV 200 ns 4.5V ≤ VCC < 5.5V, CL = 100 pF 4
Status valid time TSV 300 ns 2.5V ≤ VCC < 4.5V, CL = 100 pF 4
Program cycle time TWC 6 ms Erase/Write mode (AA and LC versions) 4
ERAL cycle time TEC 6 ms ERAL mode, 4.5V ≤ VCC ≤ 5.5V 4
WRAL cycle time TWL 15 ms WRAL mode, 4.5V ≤ VCC ≤ 5.5V 4
Endurance 1 M cycles 25°C, VCC = 5.0V (Note 2) 4

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin SOT-23, 8-lead 2x3 DFN/TDFN and 8-lead TSSOP. All packages are Pb-free (Matte Tin) finish. 1

CAD (KiCad official)

  • Symbol: 93LC56C-I
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: 93lc56c-i-etched.step / 93lc56c-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 93lc56c-i.step / 93lc56c-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (36 pp, sha256 f9a7698e3531a357, retrieved 2026-10-20, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF