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8SLVD1208NBGI

Public Made by Adom

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RENESAS Clock Buffers, Drivers, Distributors, VQFN-28(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentclock-timing8slvd1208nbgifactory-2.0.0extractor-text

Verified 8SLVD1208NBGI

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier lcsc, 29 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: 8SLVD1208NBGI · VQFN-28(5x5) · 29 pins
  • ✓copper: 29 copper pads, none touching another net
  • ✓datasheet: all 29 pin names found in the 21-page datasheet
  • ✓distributor: lcsc C6481873, digikey 6690-8SLVD1208NBGI-ND, mouser 972-8SLVD1208NBGI
  • ✓family: QFN-28-1EP_5x5mm_P0.5mm_EP3.35x3.35mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-ax7ea1p4/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 29 pins = 29 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 29 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ 8slvd1208nbgi.kicad_sym✓ 8slvd1208nbgi.kicad_mod✓ 8slvd1208nbgi.step
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Ray Publish 0.1.0 78fa3d1 2d ago

8SLVD1208NBGI

RENESAS · Clock Buffers, Drivers, Distributors · VQFN-28(5x5)

8SLVD1208NBGI from RENESAS, in a VQFN-28(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Power ground supply pin.
2 Q7 output Differential output pair 7 with LVDS interface levels.
3 nQ7 output Inverting differential output pair 7 with LVDS interface levels.
4 SEL input Reference select control pin with LVCMOS/LVTTL interface levels; 0 selects PCLK0/nPCLK0 and 1 selects PCLK1/nPCLK1, and an open pin disables the input buffers and holds the outputs static.
5 PCLK1 input Non-inverting differential clock/data input with internal pulldown.
6 nPCLK1 input Inverting differential clock/data input that defaults to VDD/2 when left floating.
7 VREF1 output Bias voltage reference for the PCLK1 and nPCLK1 inputs.
8 VDD power_in Power supply pin; the device is characterized for 2.5V ± 5% (2.375V to 2.625V).
9 PCLK0 input Non-inverting differential clock/data input with internal pulldown.
10 nPCLK0 input Inverting differential clock/data input that defaults to VDD/2 when left floating.
11 VREF0 output Bias voltage reference for the PCLK0 and nPCLK0 inputs.
12 Q0 output Differential output pair 0 with LVDS interface levels.
13 nQ0 output Inverting differential output pair 0 with LVDS interface levels.
14 GND power_in Power ground supply pin.
15 VDD power_in Power supply pin; the device is characterized for 2.5V ± 5% (2.375V to 2.625V).
16 Q1 output Differential output pair 1 with LVDS interface levels.
17 nQ1 output Inverting differential output pair 1 with LVDS interface levels.
18 Q2 output Differential output pair 2 with LVDS interface levels.
19 nQ2 output Inverting differential output pair 2 with LVDS interface levels.
20 Q3 output Differential output pair 3 with LVDS interface levels.
21 nQ3 output Inverting differential output pair 3 with LVDS interface levels.
22 Q4 output Differential output pair 4 with LVDS interface levels.
23 nQ4 output Inverting differential output pair 4 with LVDS interface levels.
24 Q5 output Differential output pair 5 with LVDS interface levels.
25 nQ5 output Inverting differential output pair 5 with LVDS interface levels.
26 Q6 output Differential output pair 6 with LVDS interface levels.
27 nQ6 output Inverting differential output pair 6 with LVDS interface levels.
28 VDD power_in Power supply pin; the device is characterized for 2.5V ± 5% (2.375V to 2.625V).
29 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer RENESAS
Package VQFN-28(5x5)
Category Clock/Timing
Pins 29

CAD (KiCad official)

  • Symbol: 8SLVD1208NBGI
  • Footprint: Package_DFN_QFN:QFN-28-1EP_5x5mm_P0.5mm_EP3.35x3.35mm
  • 3D model: VQFN-28(5x5) (KiCad packages3D, STEP)
  • 3D model files: 8slvd1208nbgi-etched.step / 8slvd1208nbgi-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 8slvd1208nbgi.step / 8slvd1208nbgi.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: RENESAS datasheet (21 pp, sha256 f4803109c493df1e, retrieved 2026-10-31, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF