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88Q2112-A2-NYD2A000-P123
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Marvell Tech Ethernet Transceivers, TQFN-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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88Q2112-A2-NYD2A000-P123
Marvell Tech · Ethernet Transceivers · TQFN-48(7x7)
88Q2112-A2-NYD2A000-P123 from Marvell Tech, in a TQFN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RSET | input | Constant voltage reference; requires an external 4.99 k 1% resistor connected to VSS. |
| 2 | HSDACP | passive | Test pin; must be left floating. |
| 3 | HSDACN | passive | Test pin; must be left floating. |
| 4 | MDIP | bidirectional | Media dependent interface positive; used for transmit and receive in 100/1000BASE-T1 mode. |
| 5 | MDIN | bidirectional | Media dependent interface negative; used for transmit and receive in 100/1000BASE-T1 mode. |
| 6 | AVDD33 | power_in | Analog supply, 3.3V. |
| 7 | ATP | passive | Test pin; must be left floating. |
| 8 | ATN | passive | Test pin; must be left floating. |
| 9 | AVDD18 | power_in | Analog supply, 1.8V; can be supplied externally or via the 1.8V internal regulator and supplies XTAL_IN/XTAL_OUT. |
| 10 | XTAL_OUT | output | 25 MHz ±100 ppm crystal reference output; leave floating when no crystal is connected. |
| 11 | VSSC | power_in | XTAL ground. |
| 12 | XTAL_IN | input | 25 MHz ±100 ppm crystal or oscillator reference input; AC couple with 0.1 nF when driven directly and not 2.5V/3.3V tolerant. |
| 13 | VDD33 (REG_IN) | power_in | Analog supply for the internal regulator, 3.3V; must be left floating (no connect) if the internal regulator is not used. |
| 14 | VDD18_OUT | power_out | Internal regulator output, 1.8V; must connect to the 1.8V plane feeding AVDD18 when the internal regulator is used, otherwise left floating. |
| 15 | AVDD18_IN | power_in | Regulator input, 1.8V; supply input for the internal DVDD regulator. |
| 16 | DVDD_OUT | power_out | Internal regulator output, 0.9V; must connect to the DVDD plane when the internal regulator is used, otherwise left floating. |
| 17 | DVDD | power_in | Digital core supply, 0.9V; can be supplied externally or via the 0.9V internal regulator. |
| 18 | RXD[3] | output | RGMII receive data bit 3; sampled on the RCLK rising edge only in 100BASE-T1 and on both RCLK edges in 1000BASE-T1. |
| 19 | RXD[2] | output | RGMII receive data bit 2; sampled on the RCLK rising edge only in 100BASE-T1 and on both RCLK edges in 1000BASE-T1. |
| 20 | RXD[1] | output | RGMII receive data bit 1; sampled on the RCLK rising edge only in 100BASE-T1 and on both RCLK edges in 1000BASE-T1. |
| 21 | RXD[0] | output | RGMII receive data bit 0; sampled on the RCLK rising edge only in 100BASE-T1 and on both RCLK edges in 1000BASE-T1. |
| 22 | RXC | output | RGMII receive control signal (RX_CTL), presented according to the RGMII timing mode requirements. |
| 23 | RCLK | output | RGMII receive clock output; 25 MHz in 100BASE-T1 and 125 MHz in 1000BASE-T1, both ±50 ppm. |
| 24 | VDDO | power_in | Digital I/O supply, 3.3V, 2.5V or 1.8V; must be supplied externally when 2.5V or 3.3V. |
| 25 | TCLK | input | RGMII transmit clock input; 25 MHz for 100BASE-T1 or 125 MHz for 1000BASE-T1, both ±50 ppm tolerance. |
| 26 | TXC | input | RGMII transmit control signal (TX_CTL), presented according to the RGMII timing mode requirements. |
| 27 | TXD[0] | input | RGMII transmit data bit 0; sampled on the TCLK rising edge only in 100BASE-T1 and on both TCLK edges in 1000BASE-T1. |
| 28 | TXD[1] | input | RGMII transmit data bit 1; sampled on the TCLK rising edge only in 100BASE-T1 and on both TCLK edges in 1000BASE-T1. |
| 29 | TXD[2] | input | RGMII transmit data bit 2; sampled on the TCLK rising edge only in 100BASE-T1 and on both TCLK edges in 1000BASE-T1. |
| 30 | TXD[3] | input | RGMII transmit data bit 3; sampled on the TCLK rising edge only in 100BASE-T1 and on both TCLK edges in 1000BASE-T1. |
| 31 | SOP | output | SGMII transmit data positive output; 1.25 GBaud. |
| 32 | SON | output | SGMII transmit data negative output; 1.25 GBaud. |
| 33 | AVDD18 | power_in | Analog supply, 1.8V; can be supplied externally or via the 1.8V internal regulator. |
| 34 | SIP | input | SGMII receive data positive input; 1.25 GBaud. |
| 35 | SIN | input | SGMII receive data negative input; 1.25 GBaud. |
| 36 | RESETn | input | Hardware reset, active-low; 0 = reset, 1 = normal operation. |
| 37 | INTn | output | Interrupt output, open-drain. |
| 38 | MDC | input | Management interface clock; maximum frequency 12.5 MHz and a continuous clock is not required. |
| 39 | MDIO | bidirectional | Management interface data; requires a pull-up resistor of 1.5 k to 10 k. |
| 40 | VDDO | power_in | Digital I/O supply, 3.3V, 2.5V or 1.8V; must be supplied externally when 2.5V or 3.3V. |
| 41 | TX_ENABLE | bidirectional | Tx enable/GPIO/LED; an input by default used to block Tx packets, and can also be used as a GPIO/LED. |
| 42 | GPIO | bidirectional | GPIO/LED output or SyncE recovered clock output. |
| 43 | DVDD | power_in | Digital core supply, 0.9V; can be supplied externally or via the 0.9V internal regulator. |
| 44 | WAKE_IN | input | Local wake-up input; leave floating when LPSD is not used. |
| 45 | INH | output | Output that controls the enable of the external regulator; leave floating when LPSD is not used. |
| 46 | VLPR | power_in | Regulated supply derived from the battery that powers the energy detect sensing circuit and the INH I/O. |
| 47 | VLPF | passive | Connect to the external battery circuit (see Figure 9); leave floating when LPSD is not used. |
| 48 | TSTPT | passive | DC test point; must be left floating. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Marvell Tech |
| Package | TQFN-48(7x7) |
| Category | Interface |
| Pins | 49 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DVDD supply voltage, absolute maximum | VDD | 1 | V | 201 | |||
| RSET resistor tolerance | RSET | -1 | 1 | % | Resistor connected to VSS; printed as ±1% Tolerance | 202 | |
| Battery voltage (LPSD) | VBAT | 6 | 12 | 28 | V | 41 | |
| Standby current (LPSD) | ISTANDBY | 50 | A | Battery voltage = 12V | 41 | ||
| Latency from MDI signals to INH assertion | TMDI,LAT | 20 | s | Normal link | 41 | ||
| INH pin source current | IINH | 50 | A | 41 | |||
| INH pin output high voltage | VINH | 1.4 | 1.9 | V | 41 | ||
| Analog 3.3V supply current, IEEE power down | IAVDDR | 5 | 5 | mA | IEEE Power Down | 205 | |
| Digital I/O supply current, IEEE power down | IVDDO | 2 | 4 | mA | IEEE Power Down, VDDO = 3.3V | 206 | |
| Digital I/O supply current, RGMII with traffic | IVDDO | 8 | 10 | mA | RGMII with traffic 100BASE-T1, VDDO = 3.3V | 206 | |
| Digital I/O supply current, SGMII with traffic | IVDDO | 2 | 4 | mA | SGMII with traffic 1000BASE-T1, VDDO = 3.3V | 206 | |
| WAKE_IN pin pulse width to wake-up | TWAKE,PW | 101 | s | 41 | |||
| Digital I/O supply current, IEEE power down | IVDDO | 2 | mA | IEEE Power Down, VDDO = 2.5V | 206 | ||
| Digital I/O supply current, IEEE power down | IVDDO | 1 | mA | IEEE Power Down, VDDO = 1.8V | 206 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | Abs | MDIP/N[1:0] 1000BASE-T1 mode TBD, TBD V+/VVIDIFF Absolute Peak Differential | 208 | |
| contacts | copper | The copper interface consists of the MDIP/N pins that connect to the physical media for | 31 |
CAD (KiCad official)
- Symbol:
88Q2112-A2-NYD2A000-P123 - Footprint:
Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm - 3D model: TQFN-48(7x7) (KiCad packages3D, STEP)
- 3D model files:
88q2112-a2-nyd2a000-p123-etched.step/88q2112-a2-nyd2a000-p123-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);88q2112-a2-nyd2a000-p123.step/88q2112-a2-nyd2a000-p123.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Marvell Tech datasheet (233 pp, sha256
dc9e6960df0900d3, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).