8305AGILF

{
  "slug": "8305agilf",
  "version": "0.1.0",
  "type": "component",
  "description": "RENESAS Clock Buffers, Drivers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "clock and timing",
    "8305agilf",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "8305agilf.kicad_sym",
    "8305agilf.kicad_mod",
    "8305agilf.glb",
    "8305agilf.step",
    "8305agilf.lbr",
    "docs/hero.png",
    "docs/8305agilf-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "8305agilf-hero.glb",
    "8305agilf-hero.overlay.json",
    "8305agilf-etched.glb"
  ],
  "component": {
    "mpn": "8305AGILF",
    "manufacturer": "RENESAS",
    "package": "TSSOP-16",
    "pin_count": 16,
    "category": "Clock and Timing",
    "subcategory": "Clock Buffers, Drivers",
    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/c470eb596991a0386fabcdabbaab9bad.pdf",
    "parts": {
      "symbol": "8305agilf.kicad_sym",
      "footprint": "8305agilf.kicad_mod",
      "model_3d": "8305agilf-hero.glb",
      "model_3d_plain": "8305agilf-etched.glb",
      "model_3d_step": "8305agilf-etched.step",
      "model_3d_step_plain": "8305agilf.step",
      "lbr": "8305agilf.lbr"
    },
    "distributor_links": {
      "lcsc": "C1520055",
      "digikey": "800-1947-5-ND",
      "mouser": "972-8305AGILF"
    },
    "distributor_check": {
      "checked_at": "2026-10-28T15:50:37Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "800-1947-5-ND",
        "status": "found"
      },
      "mouser": {
        "pn": "972-8305AGILF",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "GND",
        "type": "power_in",
        "description": "Power supply ground."
      },
      {
        "number": "2",
        "name": "OE",
        "type": "input",
        "description": "Output enable pin with internal pull-up: when LOW the outputs are in the active state, and when HIGH the outputs are in the high impedance state, with LVCMOS/LVTTL interface levels."
      },
      {
        "number": "3",
        "name": "VDD",
        "type": "power_in",
        "description": "Core power supply."
      },
      {
        "number": "4",
        "name": "CLK_EN",
        "type": "input",
        "description": "Synchronized clock enable with internal pull-up: when HIGH the clock outputs follow the clock input, and when LOW the clock outputs are forced LOW, with LVCMOS/LVTTL interface levels."
      },
      {
        "number": "5",
        "name": "CLK",
        "type": "input",
        "description": "Non-inverting differential clock input with internal pull-down, used when CLK_SEL is HIGH."
      },
      {
        "number": "6",
        "name": "nCLK",
        "type": "input",
        "description": "Inverting differential clock input with internal pull-up and pull-down, defaulting to VDD/2 when left floating."
      },
      {
        "number": "7",
        "name": "CLK_SEL",
        "type": "input",
        "description": "Clock select input with internal pull-up: when HIGH it selects the CLK/nCLK differential input, and when LOW it selects the LVCMOS_CLK input, with LVCMOS/LVTTL interface levels."
      },
      {
        "number": "8",
        "name": "LVCMOS_CLK",
        "type": "input",
        "description": "Single-ended LVCMOS/LVTTL clock input with internal pull-down, used when CLK_SEL is LOW."
      },
      {
        "number": "9",
        "name": "GND",
        "type": "power_in",
        "description": "Power supply ground."
      },
      {
        "number": "10",
        "name": "Q3",
        "type": "output",
        "description": "LVCMOS/LVTTL clock output 3."
      },
      {
        "number": "11",
        "name": "VDDO",
        "type": "power_in",
        "description": "Output supply voltage for Q0 to Q3."
      },
      {
        "number": "12",
        "name": "Q2",
        "type": "output",
        "description": "LVCMOS/LVTTL clock output 2."
      },
      {
        "number": "13",
        "name": "GND",
        "type": "power_in",
        "description": "Power supply ground."
      },
      {
        "number": "14",
        "name": "Q1",
        "type": "output",
        "description": "LVCMOS/LVTTL clock output 1."
      },
      {
        "number": "15",
        "name": "VDDO",
        "type": "power_in",
        "description": "Output supply voltage for Q0 to Q3."
      },
      {
        "number": "16",
        "name": "Q0",
        "type": "output",
        "description": "LVCMOS/LVTTL clock output 0."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The MPN 8305AGILF is the lead-free tape-and-reel ordering variant of the ICS8305I in the 16-lead TSS"
        ],
        "pages_sent": 17,
        "cost_usd": 0.0266,
        "at": "2026-10-28T15:50:07"
      },
      "datasheet": {
        "url": "https://datasheet.lcsc.com/datasheet/pdf/c470eb596991a0386fabcdabbaab9bad.pdf",
        "pages": 17,
        "sha256": "d908743cb8e9fa41",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "8305agilf.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.4,
          5.0,
          1.1
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "6ad5e98224d02a427d9a6b929a28dbc158b9925fba5adec12db05079f1016948",
        "checked": "2026-10-28",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "8305agilf-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.4,
          5.0,
          1.1
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "4c2fd0bc61f57f75d5d3b7a1e26646fd2e3350780365a9ef0671f6ad739895a7",
        "checked": "2026-10-28",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}